正弦信号与二选一选择器设计

这是eda的作品。LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_UNSIGNED.all; ENTITY singt IS PORT ( clk : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END; ARCHITECTURE dacc OF singt IS component sin_rom PORT ( address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END component; SIGNAL Q1 : STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN Q1<=Q1+1; END IF; END PROCESS; u1:sin_rom port map(address=>Q1,q=>DOUT,inclock=>clk); end;