Debug Access Port
ARM DDI 0314C3 Copyright © 2004-2006 ARM Limited. All rights reserved. 1-3
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1.1.1 Structure
The SWJ-DP consists of a wrapper around the JTAG-DP and SW-DP. Its function is to
select JTAG or SWD as the connection mechanism and enable either JTAG-DP or
SW-DP as the interface to the DAP.
1.1.2 Operation
SWJ-DP enables an Application Specific Integrated Circuit (ASIC) to be designed
which can be used in systems that require either a JTAG interface or a SWD interface.
There is a trade-off between the number of pins used and compatibility with existing
hardware and test equipment. There are several scenarios where the use of a JTAG
debug interface must be maintained:
• to enable inclusion in an existing scan chain, generally on-chip TAPs used for test
or other purposes.
• to enable the device to be cascaded with legacy devices which use JTAG for debug
• to enable use of existing debug hardware with the corresponding test TAPs, for
example, in Automatic Test Equipment (ATE).
An ASIC fitted with SWJ-DP support can be connected to legacy JTAG equipment
without any requirement to make changes. If a SWD tool is available, only two pins are
required, instead of the usual four used for JTAG. Two pins are therefore released for
alternative use.
These two pins can only be used when there is no conflict with their use in JTAG mode.
In addition, to support use of SWJ-DP in a scan chain with other JTAG devices, the
default state after reset must be to use these pins for their JTAG function. If the direction
of the alternative function is compatible with being driven by a JTAG debug device, the
transition to a shift state can be used to transition from the alternative function to JTAG
mode.
The alternate function cannot be used while the ASIC is being used in JTAG debug
mode.
The switching scheme is arranged so that, provided there is no conflict on the TDI and
TDO pins, a JTAG debugger is able to connect by sending a specific sequence.
The connection sequence used for SWD is safe when applied to the JTAG interface,
even if hot-plugged, enabling the debugger to continually retry its access sequence. A
sequence with
TMS=1
ensures that JTAG-DP, SW-DP, and the watcher circuit are in a
known reset state. The pattern used to select SWD has no effect on JTAG targets.
SWJ-DP is compatible with a free-running TCK, or a gated clock which is supplied by
the external tools.
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