readme - Triple Speed Ethernet Design
Overview:
=========
This design is provided to showcase the design example running on the Nios development boards and highlights many of the
advanced features of the Nios II processor, Triple Speed Ethernet and the Scatter Gather DMA.
Contents of the System:
=======================
- Nios II/f Core
- JTAG Debug Module (Level 1)
- DDR SDRAM Controller (128MB)
- CFI Flash Memory Interface (64MB)
- Descriptor memories (On Chip Memory)
- JTAG UART
- UART (RS-232)
- Two Timers
- Ethernet Interface
- LED PIO
- Push Button PIO
- Performance Counter
- System ID Peripheral
- PLLs
Supported Software Examples:
============================
- Blank Project
- Hello World
- Board Diagnostic
- Count Binary
- Hello Free-Standing
- Hello MicroC/OS II
- Hello World Small
- Memory Test
- Simple Sockets Server *
- Web Server *
- The 3c120 development kit board is using RGMII interface for the PHY connection,
the TSE initialization need to updated to turn on the timing control on the
Marvell PHY. Please refer to the simple_socket_server_tse_3c120_rgmii and
web_server_tse_3c120_rgmii for the details.
Further Notes:
==============
- The top level of this design is the HDL file generated around the Qsys Editor design. This wrapper performs the following functions:
1.) Renaming the DDR-associated pins from Qsys Editor to match the timing assignments produced by the DDR megafunction.
2.) If you modify and regenerate the Qsys Editor design, the port list of the Qsys Editor instance may change.
You must manually edit the HDL wrapper file to rectify any discrepancies.
- This Quartus II project contains assignments that match the port names produced by Qsys Editor.
If you add or modify Qsys Editor components, the pin assignments may no longer be valid.
To view the Assignment Editor in the Quartus II software, in the Assignments menu, click "Assignment Editor".
- This design contains the DDR memory and Triple Speed Ethernet components. Any design containing these cores must be re-generated
in Qsys Editor before re-compiling it in Quartus if the installation path to the Altera toolchain has changed since it was
last generated. This is because these cores make use of RTL libraries that are referenced using absolute paths. The re-generation
process will update these absolute paths.
Attempting to recompile in Quartus II without regenerating will result in an error of the following form during Quartus II Analysis and
Synthesis:
Error: Node instance "ddr_control" instantiates undefined entity "auk_ddr_controller"
- Only single bank DDR memory is used as program and data memory. Thus, memtest should not run on
the DDR memory bank as could cause destructive effect to the program code and data.
- The current version of the Nios II EDS hardware design example uses an HDL
file as the top level of the design hierarchy. If you would like to use a
schematic-based top level instead (BDF), follow the steps listed below.
1) In the Quartus II software, open the top-level HDL file (.v or .vhd) for
the design.
2) Create a symbol for the HDL file by clicking
File -> Create/Update -> Create Symbol Files for Current File
3) Create a new BDF file by clicking
File -> New -> Block Diagram/Schematic File.
4) Instantiate the symbol in the BDF by double-clicking in the empty space
of the BDF file and selecting "Project -> <symbol filename>"
5) Instantiate pins in the BDF by double-clicking empty space, then
typing "input", "output", or "bidir".
6) Rename the pins and connect them to the appropriate ports on the symbol.
7) Save the BDF as a unique filename.
8) Set the BDF as your top level entity by clicking:
Project -> Set as Top-Level Entity
9) Recompile the Quartus II project.
- This example design should be used with any of the Altera's Partner Development Board Daughter Cards
(http://www.altera.com/products/devkits/kit-daughter_boards.jsp) listed below:
1) 10/100 Ethernet PHY Daughter Card with National Semiconductor PHY (http://www.morethanip.com/boards_10_100_dp83848.htm)
2) 10/100/1000 Ethernet PHY Daughter Board with Marvell PHY (http://www.morethanip.com/boards_10_100_1000_88E1111.htm)
3) 10/100/1000 Ethernet PHY Daughter Card with National Semiconductor PHY (http://www.morethanip.com/boards_10_100_1000_dp83865.htm)
- For more information, please refer to http://www.altera.com/support/examples/nios2/exm-nios2.html
Triple-Speed Ethernet(tse)FPGA软核MAC官方实例 （372个子文件） 
tse_my_system.c 328B tse_my_system.c 328B create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-app 3KB create-this-bsp 868B create-this-bsp 854B create-this-bsp 828B create-this-bsp 421B create-this-bsp 415B altmemddr2_ynbnbsh3_phy_summary.csv 345B altera_nios2_qsys_gt36nw2m_ic_tag_ram.dat 7KB altera_nios2_qsys_gt36nw2m_dc_tag_ram.dat 5KB altera_nios2_qsys_gt36nw2m_ociram_default_contents.dat 2KB altera_nios2_qsys_gt36nw2m_bht_ram.dat 516B altera_nios2_qsys_gt36nw2m_rf_ram_b.dat 292B altera_nios2_qsys_gt36nw2m_rf_ram_a.dat 292B altera_avalon_jtag_uart_2pkhqydp_input_stream.dat 9B altera_avalon_uart_zjyzji6n_input_data_stream.dat 5B altera_avalon_uart_zjyzji6n_input_data_mutex.dat 2B altera_avalon_jtag_uart_2pkhqydp_input_mutex.dat 2B altera_avalon_jtag_uart_2pkhqydp_output_stream.dat 0B altera_nios2_qsys_gt36nw2m.do 10KB tserd_3c120.done 25B altera_avalon_onchip_memory2_fyilba6c.hex 40KB altera_nios2_qsys_gt36nw2m_ic_tag_ram.hex 18KB altera_nios2_qsys_gt36nw2m_dc_tag_ram.hex 16KB altera_nios2_qsys_gt36nw2m_ociram_default_contents.hex 5KB altera_nios2_qsys_gt36nw2m_bht_ram.hex 4KB altera_nios2_qsys_gt36nw2m_rf_ram_b.hex 668B altera_nios2_qsys_gt36nw2m_rf_ram_a.hex 668B tserd_3c120.jdi 22KB altera_nios2_qsys_gt36nw2m_ic_tag_ram.mif 14KB altera_nios2_qsys_gt36nw2m_dc_tag_ram.mif 12KB altera_nios2_qsys_gt36nw2m_ociram_default_contents.mif 6KB altera_nios2_qsys_gt36nw2m_bht_ram.mif 2KB altera_nios2_qsys_gt36nw2m_rf_ram_b.mif 558B altera_nios2_qsys_gt36nw2m_rf_ram_a.mif 558B altera_tse_mac_woff.ocp 2KB altera_tse_top_1000_base_x.ocp 2KB altera_tse_top_gen_host.ocp 2KB altera_tse_top_1000_base_x_strx_gx.ocp 2KB altera_nios2_qsys_gt36nw2m.ocp 864B tserd_3c120.pin 89KB qsys_tserd_3c120.qip 46KB tserd_3c120.qpf 1KB tserd_3c120.qsf 56KB qsys_tserd_3c120.qsys 73KB tserd_3c120.qws 548B reg.rout 24B tserd_3c120.sta.rpt 25.67MB tserd_3c120.map.rpt 12.72MB tserd_3c120.fit.rpt 3.73MB tserd_3c120.flow.rpt 9KB tserd_3c120.asm.rpt 7KB altmemddr2_ynbnbsh3_phy_ddr_timing.sdc 32KB triple_speed_ethernet_3ry6ly3p_constraints.sdc 30KB altera_nios2_qsys_gt36nw2m.sdc 4KB altera_avalon_half_rate_bridge_constraints.sdc 4KB altera_reset_controller.sdc 1KB tserd_3c120.sdc 1KB altmemddr2_ynbnbsh3_example_top.sdc 159B tserd_3c120.map.smsg 6KB tserd_3c120.fit.smsg 507B tserd_3c120.sof 3.38MB qsys_tserd_3c120.sopcinfo 894KB tserd_3c120.sta.summary 26KB tserd_3c120.fit.summary 627B tserd_3c120.map.summary 474B altera_merlin_width_adapter.sv 35KB altera_merlin_burst_adapter.sv 34KB altera_merlin_multiplexer_k7ry7iqz.sv 21KB altera_merlin_slave_agent.sv 17KB altera_merlin_master_translator.sv 15KB altera_merlin_slave_translator.sv 15KB altera_merlin_multiplexer_man45s6j.sv 13KB altera_merlin_multiplexer_2luvp2nh.sv 13KB altera_merlin_multiplexer_vh2x3wuy.sv 13KB altera_merlin_traffic_limiter.sv 13KB altera_merlin_multiplexer_ytfzs2n3.sv 12KB altera_merlin_demultiplexer_qkpwthmz.sv 11KB altera_merlin_multiplexer_dqvyatxs.sv 10KB altera_merlin_multiplexer_rwyy372l.sv 10KB altera_merlin_multiplexer_7wjxmhzx.sv 10KB altera_merlin_multiplexer_xchcxrgc.sv 10KB altera_merlin_burst_uncompressor.sv 10KB altera_tristate_controller_aggregator.sv 9KB altera_merlin_arbitrator.sv 9KB altera_tse_reset_ctrl_lego.sv 9KB altera_merlin_std_arbitrator_core.sv 9KB altera_merlin_master_agent.sv 8KB altera_merlin_router_uylwgrqd.sv 8KB altera_tristate_conduit_bridge_us35rebs.sv 7KB共 372 条
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