Cadence virtuoso smic 180工艺库 标准库 OA库 BCD库 直接使用 含PDK文件 IC617IC618

Semiconductor Manufacturing International Corporation

FIG.A1. VTH_GM VERSUS L AT WDRAWN = 20UM FOR 10V NLDMOS .............................................................................. 6

FIG.A2. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 10V NLDMOS ................................................................................ 6

FIG.A9. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 10V NLDMOS ..................................... 10

FIG.A10. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 10V NLDMOS 20/10...... 10

FIG.A11. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 10V NLDMOS 20/0.5..... 11

FIG.A12. IDLIN VERSUS T MEASURED AND SIMULATED PLOT FOR 10V NLDMOS 20/0.5 ....................................... 11

FIG.A13. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 10V NLDMOS 20/0.5 ....................................... 12

FIG.A14. VTH_GM VERSUS L AT WDRAWN = 20UM FOR 10V PLDMOS ........................................................................ 12

FIG.A15. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 10V PLDMOS .......................................................................... 13

FIG.A16. VTH_SAT VERSUS L AT WDRAWN = 20UM FOR 10V PLDMOS ....................................................................... 13

FIG.A17. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 10V PLDMOS ........................................................................ 14

FIG.A18. VTH_GM VERSUS W AT LDRAWN = 0.4UM FOR 10V PLDMOS ....................................................................... 14

FIG.A25. IDLIN VERSUS T MEASURED AND SIMULATED PLOT FOR 10V PLDMOS 20/0.4 ........................................ 18

FIG.A26. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 10V PLDMOS 20/0.4 ....................................... 18

FIG.A27. VTH_GM VERSUS L AT WDRAWN = 40UM FOR 12V NLDMOS ....................................................................... 19

FIG.A28. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 12V NLDMOS ......................................................................... 19

FIG.A29. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 12V NLDMOS ....................................................................... 20

FIG.A30. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 12V NLDMOS ....................................................................... 20

FIG.A31. VTH_GM VERSUS W AT LDRAWN = 0.9UM FOR 12V NLDMOS ...................................................................... 21

FIG.A32. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 12V NLDMOS .................................... 21

FIG.A33. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 12V NLDMOS ................................ 22

FIG.A34. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 12V NLDMOS .................................... 22

FIG.A41. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 12V PLDMOS .......................................................................... 26

FIG.A42. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 12V PLDMOS ....................................................................... 26

FIG.A43. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 12V PLDMOS ........................................................................ 27

FIG.A44. VTH_GM VERSUS W AT LDRAWN = 0.9UM FOR 12V PLDMOS ....................................................................... 27

FIG.A45. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 12V PLDMOS ..................................... 28

FIG.A46. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 12V PLDMOS ................................. 28

FIG.A47. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 12V PLDMOS ..................................... 29

FIG.A48. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 12V PLDMOS................................. 29

FIG.A49. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 12V PLDMOS 40/10 ...... 30

FIG.A50. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 12V PLDMOS 20/0.9 ..... 30

FIG.A57. VTH_GM VERSUS W AT LDRAWN = 0.8UM FOR 20V NLDMOS ...................................................................... 34

FIG.A58. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 20V NLDMOS .................................... 34

FIG.A59. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 20V NLDMOS ................................ 35

FIG.A60. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 20V NLDMOS .................................... 35

FIG.A61. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 20V NLDMOS ................................ 36

FIG.A62. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 20V NLDMOS 40/10...... 36

FIG.A63. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 20V NLDMOS 20/0.8..... 37

Semiconductor Manufacturing International Corporation

FIG.A64. IDLIN VERSUS T MEASURED AND SIMULATED PLOT FOR 20V NLDMOS 20/0.8 ....................................... 37

FIG.A65. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 20V NLDMOS 20/0.8 ....................................... 38

FIG.A72. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 20V PLDMOS ................................. 41

FIG.A73. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 20V PLDMOS ..................................... 42

FIG.A74. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 20V PLDMOS................................. 42

FIG.A75. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 20V PLDMOS 40/10 ...... 43

FIG.A76. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 20V PLDMOS 20/0.9 ..... 43

FIG.A77. IDLIN VERSUS T MEASURED AND SIMULATED PLOT FOR 20V PLDMOS 20/0.9 ........................................ 44

FIG.A78. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 20V PLDMOS 20/0.9 ....................................... 44

FIG.A79. VTH_GM VERSUS L AT WDRAWN = 40UM FOR 35V NLDMOS ....................................................................... 45

FIG.A80. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 35V NLDMOS ......................................................................... 45

FIG.A81. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 35V NLDMOS ....................................................................... 46

FIG.A88. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 35V NLDMOS 40/10...... 49

FIG.A89. VTH_GM VS. T MEASURED AND SIMULATED PLOT WITH VARIOUS VBS FOR 35V NLDMOS 20/1.15 ... 50

FIG.A90. IDLIN VERSUS T MEASURED AND SIMULATED PLOT FOR 35V NLDMOS 20/1.15 ..................................... 50

FIG.A91. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 35V NLDMOS 20/1.15 ..................................... 51

FIG.A92. VTH_GM VERSUS L AT WDRAWN = 40UM FOR 35V PLDMOS ........................................................................ 51

FIG.A93. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 35V PLDMOS .......................................................................... 52

FIG.A94. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 35V PLDMOS ....................................................................... 52

FIG.A95. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 35V PLDMOS ........................................................................ 53

FIG.A96. VTH_GM VERSUS W AT LDRAWN = 0.9UM FOR 35V PLDMOS ....................................................................... 53

FIG.A97. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 35V PLDMOS ..................................... 54

FIG.A104. IDSAT VERSUS T MEASURED AND SIMULATED PLOT FOR 35V PLDMOS 20/0.9 ....................................... 57

FIG.A105. VTH_GM VERSUS L AT WDRAWN = 40UM FOR 40V NLDMOS ....................................................................... 58

FIG.A106. VTH_GM VERSUS L AT WDRAWN = 8UM FOR 40V NLDMOS ......................................................................... 58

FIG.A107. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 40V NLDMOS ....................................................................... 59

FIG.A108. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 40V NLDMOS ....................................................................... 59

FIG.A109. VTH_GM VERSUS W AT LDRAWN = 1.35UM FOR 40V NLDMOS .................................................................... 60

FIG.A110. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 40V NLDMOS .................................... 60

FIG.A111. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 40V NLDMOS ................................ 61

FIG.A112. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 40V NLDMOS .................................... 61

FIG.A113. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 40V NLDMOS ................................ 62

FIG.A120. VTH_SAT VERSUS L AT WDRAWN = 40UM FOR 40V PLDMOS ....................................................................... 65

FIG.A121. VTH_GM VERSUS W AT LDRAWN = 10UM FOR 40V PLDMOS ........................................................................ 66

FIG.A122. VTH_GM VERSUS W AT LDRAWN = 0.7UM FOR 40V PLDMOS ....................................................................... 66

FIG.A123. IDLIN VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 40V PLDMOS ..................................... 67

FIG.A124. IDLIN VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 40V PLDMOS ................................. 67

FIG.A125. IDSAT VERSUS L WITH DIFFERENT WIDTH ARRAY AT VBS=0 FOR 40V PLDMOS ..................................... 68

FIG.A126. IDSAT VERSUS W WITH DIFFERENT LENGTH ARRAY AT VBS=0 FOR 40V PLDMOS................................. 68