发送端整体框图：
对应上面的 top_mode 模块，下面是其内部模块：
太大了，电脑桌面显示不了，截了一部分
//发送端顶层程序
module
nrf24l01_jieshou_module(clk,reset_n,key_in,miso,mosi,sclk,ce,csn,irq,one_wire,RS,RW,cont,en,l
cd_data_out);
input clk;
input reset_n;
input key_in;
input miso;
output mosi;
output sclk;
output ce;
output csn;
input irq;
inout one_wire;
output RS,RW,cont,en;
output [7:0]lcd_data_out;
wire [7:0]rx_data;
wire [2:0] Tx_data_byte;
wire [47:0]Tx_address_data;
wire nr_se_en_signal;
wire se_nr_end_signal;
wire key_en;
wire sign_temp;
wire [11:0]temph_data,templ_data;
top_mode U0(clk,reset_n,one_wire,temph_data,templ_data,sign_temp);
nrf24l01_control
U1(clk,reset_n,key_en,ce,irq,nr_se_en_signal,se_nr_end_signal,Tx_data_byte,Tx_address_data,rx
_data,{temph_data,templ_data});
send_function
U2(clk,reset_n,nr_se_en_signal,Tx_data_byte,Tx_address_data,rx_data,csn,miso,mosi,sclk,se_nr_
end_signal);
lcd U3(clk,reset_n,temph_data,templ_data,sign_temp,RS,RW,cont,en,lcd_data_out);
key_mode U4(clk,reset_n,key_in,key_en);
endmodule
//DS18B20 控制模块顶层程序
module top_mode(clk,rst,ds18b20_Q,temph_data,templ_data,sign_temp);
input clk,rst;
inout ds18b20_Q;
output [11:0] temph_data,templ_data;
output sign_temp;
wire ld,en_in,en1,en2,en5,en6,master_en,cont_end,test_end;
wire [3:0]cont_data1,cont_data2,cont_data3,cont_data6,cont_state;
wire [2:0]cont_byte;
wire [1:0]cont_bit;
wire [7:0]tmph_data,tmpl_data;
reg test_en;
//assign en_in=1'b1;
assign ld=~(en6 || cont_end);
micro_sec_out U0(clk,rst,1'b1,ld,en_in);
micro_sec_cont
U1(clk,rst,en_in,ld,cont_data1,cont_data2,cont_data3,cont_data6,en1,en2,en5,en6);
state_ctl
U2(clk,rst,test_en,cont_data1,cont_data2,cont_data3,cont_data6,en_in,en1,en2,en5,cont_state,cont
_byte,cont_bit,test_end,cont_end);
byte_trans
U3(clk,rst,cont_state,cont_byte,cont_bit,test_en,cont_end,ds18b20_Q,ds18b20_Q,tmph_data,tmpl
_data);
conversion_data U4(clk,rst,test_end,tmph_data,tmpl_data,temph_data,templ_data,sign_temp);
always @(posedge clk or negedge rst)
if(~rst)
test_en<=1'b0;
else if((~test_en & en6) || (test_en & test_end))
test_en<=~test_en;
endmodule
//
module micro_sec_out(clk,rst,en_in,ld,en_out);
input clk,rst,en_in,ld;
output en_out;
//output [3:0]cont_data;
wire [3:0] cont_data;
wire en1;
//assign en_out=en_in & cont_data[3] & cont_data[0];
//assign data_out= cont_data;
cont_5 U0(clk,rst,en_in,ld,en1);
cont_10 U1(clk,rst,en1,ld,cont_data,en_out);
endmodule
//
module
micro_sec_cont(clk,rst,en_in,ld,cont_data1,cont_data2,cont_data3,cont_data6,en1,en2,en5,en6);
input clk,rst,en_in,ld;
output en1,en2,en5,en6;
output [3:0]cont_data1,cont_data2,cont_data3,cont_data6;
wire [3:0] cont_data;
wire en1,en3,en4,en5;
wire [3:0]cont_data4,cont_data5;
cont_10 U1(clk,rst,en_in,ld,cont_data1,en1);
cont_10 U2(clk,rst,en1,ld,cont_data2,en2);
cont_10 U3(clk,rst,en2,ld,cont_data3,en3);
cont_10 U4(clk,rst,en3,ld,cont_data4,en4);
cont_10 U5(clk,rst,en4,ld,cont_data5,en5);
cont_10 U6(clk,rst,en5,ld,cont_data6,en6);
endmodule
//DS18B20 控制状态切换程序
module
state_ctl(clk,rst,test_en,cont_data1,cont_data2,cont_data3,cont_data6,en0,en1,en2,en5,cont_state,c
ont_byte,cont_bit,test_end,cont_end);
input clk,rst,test_en,en0,en1,en2,en5;
input [3:0]cont_data1,cont_data2,cont_data3,cont_data6;
output [3:0]cont_state;
output [2:0]cont_byte;
output [1:0]cont_bit;
output test_end,cont_end;
reg cont_end;
reg [3:0]cont_state;
reg [2:0]cont_byte;
reg [1:0]cont_bit;
assign test_end = cont_state[3] & cont_byte[2] & cont_byte[1] & cont_byte[0] & cont_bit[1] &
cont_end;
always @(posedge clk or negedge rst)
if(~rst)
cont_state<=4'b0000;
else if(~test_en)
cont_state<=4'b0000;
else if(cont_end & cont_bit[1])
begin
case(cont_state)
4'b0000:cont_state<=4'b0001;
4'b0001:begin
if(cont_byte==3'b111)
cont_state<=4'b0010;
else
cont_state<=4'b0001;
end
4'b0010:begin
if(cont_byte==3'b111)
cont_state<=4'b0011;
else
cont_state<=4'b0010;
end
4'b0011:cont_state<=4'b0100;
4'b0100:cont_state<=4'b0101;
4'b0101:begin
if(cont_byte==3'b111)
cont_state<=4'b0110;
else
cont_state<=4'b0101;
end
4'b0110:begin
if(cont_byte==3'b111)
cont_state<=4'b0111;
else
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