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AT89C51单片机中英文文献翻译.pdf
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AT89C51单片机中英文文献翻译.pdf
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The General Situation of AT89C51
1 The application of AT89C51
Microcontrollers are used in a multitude of commercial applications such as modems,
motor-control systems, air conditioner control systems, automotive engine and among others.
The high processing speed and enhanced peripheral set of these microcontrollers make them
suitable for such high-speed event-based applications. However, these critical application
domains also require that these microcontrollers are highly reliable. The high reliability and
low market risks can be ensured by a robust testing process and a proper tools environment
for the validation of these microcontrollers both at the component and at the system level.
Intel Platform Engineering department developed an object-oriented multi-threaded test
environment for the validation of its AT89C51 automotive microcontrollers. The goals of this
environment was not only to provide a robust testing environment for the AT89C51
automotive microcontrollers, but to develop an environment which can be easily extended and
reused for the validation of several other future microcontrollers. The environment was
developed in conjunction with Microsoft Foundation Classes (AT89C51). The paper
describes the design and mechanism of this test environment, its interactions with various
hardware/software environmental components, and how to use AT89C51.
1.1 Introduction
The 8-bit AT89C51 CHMOS microcontrollers are designed to handle high-speed
calculations and fast input/output operations. MCS 51 microcontrollers are typically used for
high-speed event control systems. Commercial applications include modems, motor-control
systems, printers, photocopiers, air conditioner control systems, disk drives, and medical
instruments. The automotive industry use MCS 51 microcontrollers in engine-control systems,
airbags, suspension systems, and antilock braking systems (ABS). The AT89C51 is especially
well suited to applications that benefit from its processing speed and enhanced on-chip
peripheral functions set, such as automotive power-train control, vehicle dynamic suspension,
antilock braking, and stability control applications. Because of these critical applications, the
market requires a reliable cost-effective controller with a low interrupt latency response,
ability to service the high number of time and event driven integrated peripherals needed in
real time applications, and a CPU with above average processing power in a single package.
The financial and legal risk of having devices that operate unpredictably is very high. Once in
the market, particularly in mission critical applications such as an autopilot or anti-lock
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braking system, mistakes are financially prohibitive. Redesign costs can run as high as a
$500K, much more if the fix means 2 back annotating it across a product family that share the
same core and/or peripheral design flaw. In addition, field replacements of components are
extremely expensive, as the devices are typically sealed in modules with a total value several
times that of the component. To mitigate these problems, it is essential that comprehensive
testing of the controllers be carried out at both the component level and system level under
worst case environmental and voltage conditions. This complete and thorough validation
necessitates not only a well-defined process but also a proper environment and tools to
facilitate and execute the mission successfully. Intel Chandler Platform Engineering group
provides post silicon system validation (SV) of various micro-controllers and processors. The
system validation process can be broken into three major parts. The type of the device and its
application requirements determine which types of testing are performed on the device.
1.2 The AT89C51 provides the following standard features:
4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five
vector two-level interrupt architecture, a full duple serial port, on-chip oscillator and clock
circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero
frequency and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port and interrupt sys -tem to continue
functioning. The Power-down Mode saves the RAM contents but freezes the oscillator
disabling all other chip functions until the next hardware reset.
![](https://csdnimg.cn/release/download_crawler_static/86121948/bg3.jpg)
Figure 1-2-1 Block Diagram
1.3 Pin Description
VCC: Supply voltage.
GND: Ground.
Port 0: Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin
can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data
bus during accesses to external program and data memory. In this mode P0 has internal pull
ups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes
during program verification. External pull ups are required during program verification.
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