LIBRARY IEEE; -- 半加器描述( 2 ):真值表描述方法
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT (a, b : IN STD_LOGIC;
co, so : OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder IS
SIGNAL abc: STD_LOGIC_VECTOR (1 DOWNTO 0); -- 定义标准逻辑矢量
BEGIN
abc <= a & b; --a 相并 b, 即 a 与 b 并置操作,获得二维矢量
PROCESS(abc) BEGIN
CASE abc IS
WHEN ”00” => so <= ‘0’; co <= ‘0’;
WHEN ”01” => so <= ‘1’; co <= ‘0’;
WHEN ”10” => so <= ‘1’; co <= ‘0’;
WHEN ”11” => so <= ‘0’; co <= ‘1’;
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END ARCHITECTURE fh1;
【例 3-
5 】
输入 输出
a b so co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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