I2C_Software_Htu21d

/** ****************************************************************************** * @file stm32f10x_rcc.c * @author MCD Application Team * @version V3.5.0 * @date 11-March-2011 * @brief This file provides all the RCC firmware functions. ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f10x_rcc.h" /** @addtogroup STM32F10x_StdPeriph_Driver * @{ */ /** @defgroup RCC * @brief RCC driver modules * @{ */ /** @defgroup RCC_Private_TypesDefinitions * @{ */ /** * @} */ /** @defgroup RCC_Private_Defines * @{ */ /* ------------ RCC registers bit address in the alias region ----------- */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define CR_OFFSET (RCC_OFFSET + 0x00) #define HSION_BitNumber 0x00 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) /* Alias word address of PLLON bit */ #define PLLON_BitNumber 0x18 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) #ifdef STM32F10X_CL /* Alias word address of PLL2ON bit */ #define PLL2ON_BitNumber 0x1A #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) /* Alias word address of PLL3ON bit */ #define PLL3ON_BitNumber 0x1C #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) #endif /* STM32F10X_CL */ /* Alias word address of CSSON bit */ #define CSSON_BitNumber 0x13 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) /* --- CFGR Register ---*/ /* Alias word address of USBPRE bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x04) #ifndef STM32F10X_CL #define USBPRE_BitNumber 0x16 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) #else #define OTGFSPRE_BitNumber 0x16 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) #endif /* STM32F10X_CL */ /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ #define BDCR_OFFSET (RCC_OFFSET + 0x20) #define RTCEN_BitNumber 0x0F #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x24) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) #ifdef STM32F10X_CL /* --- CFGR2 Register ---*/ /* Alias word address of I2S2SRC bit */ #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) #define I2S2SRC_BitNumber 0x11 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) /* Alias word address of I2S3SRC bit */ #define I2S3SRC_BitNumber 0x12 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) #endif /* STM32F10X_CL */ /* ---------------------- RCC registers bit mask ------------------------ */ /* CR register bit mask */ #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) #define CR_HSEBYP_Set ((uint32_t)0x00040000) #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) #define CR_HSEON_Set ((uint32_t)0x00010000) #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) /* CFGR register bit mask */ #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) #else #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) #endif /* STM32F10X_CL */ #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) #define CFGR_SWS_Mask ((uint32_t)0x0000000C) #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) /* CSR register bit mask */ #define CSR_RMVF_Set ((uint32_t)0x01000000) #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) /* CFGR2 register bit mask */ #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) #endif #ifdef STM32F10X_CL #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) #endif /* STM32F10X_CL */ /* RCC Flag Mask */ #define FLAG_Mask ((uint8_t)0x1F) /* CIR register byte 2 (Bits[15:8]) base address */ #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) /* CIR register byte 3 (Bits[23:16]) base address */ #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) /* CFGR register byte 4 (Bits[31:24]) base address */ #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) /* BDCR register base address */ #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) /** * @} */ /** @defgroup RCC_Private_Macros * @{ */ /** * @} */ /** @defgroup RCC_Private_Variables * @{ */ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; /** * @} */ /** @defgroup RCC_Private_FunctionPrototypes * @{ */ /** * @} */ /** @defgroup RCC_Private_Functions * @{ */ /** * @brief Resets the RCC clock configuration to the default reset state. * @param None * @retval None */ void RCC_DeInit(void) { /* Set HSION bit */ RCC->CR |= (uint32_t)0x00000001; /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ #ifndef STM32F10X_CL RCC->CFGR &= (uint32_t)0xF8FF0000; #else RCC->CFGR &= (uint32_t)0xF0FF0000; #endif /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFFF; /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ RCC->CFGR &= (uint32_t)0xFF80FFFF; #ifdef STM32F10X_CL /* Reset PLL2ON and PLL3ON bits */ RCC->CR &= (uint32_t)0xEBFFFFFF; /* Disable all