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CH7033B

Full datasheet

201-1000-024 Rev1.32 04/11/2016 1

Chrontel

CH7033B HDTV/VGA/DVI Encoder

FEATURES

GENERAL DESCRIPTION

 DVI encoder support up to 1080p

 Supports Component YPrPb (HDTV) up to 1080p

and analog RGB (VGA) monitor up to 1920x1080

resolution

 Support scaled and bypassed video streams output

from VGA/HDTV and DVI interfaces

simultaneously

 Three 10-bit high speed DACs

 SPDIF audio interface supports either 16-bit or 20-

bit stereo data for up to 192kHz/2ch

 Support 2 channel I2S digital audio input for up to

24-bit data stream (32kHz, 44.1kHz, 48kHz,

88.2kHz, 96kHz, 176.4kHzand 192kHz)

 DDC master for reading EDID

 Hot plug detection for DVI

 TV/Monitor connection detect capability. DACs can

be switched off through programming internal

registers

 Pixel-level color enhancement for brightness,

contrast, hue and saturation adjustment for HDTV

and VGA output

 On-chip frame buffer supports frame rate conversion

provides the graphic controller the flexibility of

video timing output

 Advanced scaling engine to upsize/downsize input

resolution for DVI display up to 1080p, VGA up to

1920 x1080 and HDTV up to 1080p

 Supports 8/12/16/18/24-bit parallel interface input

for either RGB format (RGB-565, RGB-666 or

RGB-888 and etc.) or YCrCb format (ITU-R 656 or

ITU-R 601). 80/86 MPU interface and DE only

mode are also supported.

 Wide range of input resolutions support for up to

1366x768 (i.e. 640x480, 720x480, 720x576,

800x600, 1024x600, 1024x768, 1280x800, and etc.)

 Image display rotation support at 90/180/270 degree

or flipped in horizontal/vertical position

 Pixel clock input frequency support for up to 165

MHz

 IO Supply Voltages from 1.2V to 3.3V and

SPC/SPD Supply Voltages from 1.8V to 3.3V.

 Programmable power management

 Device fully programmable through serial port or

can automatically load firmware from Chrontel Boot

ROM (CH9904)

 Offered in a 88-pin QFN package

The Chrontel CH7033B is specifically designed for

consumer electronics device and PC markets which

multiple high definition content display formats are

required. With its advanced video encoder, flexible

scaling engine and easy-to-configure audio interface, the

CH7033B satisfies manufactures’ products display

requirements and reduce their costs of development and

time-to-market.

High quality high-bandwidth uncompressed video like

DVI and YPrPb components or legacy VGA analog

display are supported by the device’s color format

converter. The 3 high-performance, 10-bit DACs can be

used for either HDTV display or VGA output depending

on manufactures’ products specification. The device is

compliant with EIA770-3 and SMPTE

274M/293M/296M standards and supports HDTV

resolution for up to 1080p. The CH7033B has the ability

to generate composite syncs if required by the RGB

monitor.

The CH7033B’s 24-bit parallel bus accepts a wide range

of input data formats from the graphic controller. The

built-in video port supports 8/12/16/18/24-bit data

interface as well as 80/86 MPU interface. The video

format conversion module is capable of translating digital

RGB-565, RGB-666, RGB-888 or YCrCb (ITU-R 656,

ITU-R 601) signal to the DVI signal, combining with the

audio stream. The input digital signal also can be

transformed by the DACs for HDTV or VGA analog

outputs. The device’s video capture block supports input

display resolution for up to 1366x768 which can be either

interlaced or non-interlaced timing.

The CH7033B has incorporated a high speed SDRAM

that allows manufactures to design their products to

achieve simultaneous display digital signal and analog

signal. Leverage the benefit of the framebuffer, the

device’s sophisticated scaler is able to produce two same

video content, which will be routed to separate output

driver for display. Frame Rate Conversion is embedded

in the scaler; it can maximize the native input resolution

up to 1080p for HD display. Furthermore the CH7033B

provides additional image manipulation features

including image rotation that can be controlled through

programming internal registers.

The CH7033B supports both SPDIF and 2-channel I²S

CHRONTEL CH7033B

4 201-1000-024 Rev1.32 04/11/2016

TABLE OF CONTENTS

FEATURES ....................................................................................................................................... 1

GENERAL DESCRIPTION ................................................................................................................. 1

APPLICATION .................................................................................................................................. 2

1.0 PIN-OUT ............................................................................................................................ 6

1.1 Package Diagram ........................................................................................................................................... 6

1.2 Pin Description .............................................................................................................................................. 7

2.0 FUNCTIONAL DESCRIPTION ............................................................................................ 10

2.1 Video Input .................................................................................................................................................. 10

2.1.1 Overview ............................................................................................................................................. 10

2.1.2 Input Clock and Data Timing Diagram................................................................................................ 10

2.1.3 Input data voltage ................................................................................................................................ 11

2.1.4 Input data format .................................................................................................................................. 12

2.2 Audio Input .................................................................................................................................................. 13

2.2.1 SPDIF Input ......................................................................................................................................... 13

2.2.2 I2S Input .............................................................................................................................................. 13

2.3 DAC Output ................................................................................................................................................. 14

2.3.1 HDTV Output ...................................................................................................................................... 14

2.3.2 VGA Output......................................................................................................................................... 14

2.3.3 DAC output Configuration .................................................................................................................. 15

2.3.4 DAC single/double termination ........................................................................................................... 15

2.3.5 TV connection detect ........................................................................................................................... 15

2.3.6 Picture enhancement ............................................................................................................................ 15

2.4 DVI Output .................................................................................................................................................. 15

2.5 EDID Buffer ................................................................................................................................................ 17

2.6 Testing Functions and Power Down Mode .................................................................................................. 17

2.6.1 Test Pattern Select ............................................................................................................................... 17

2.6.2 SDRAM Power Down ......................................................................................................................... 17

3.0 REGISTER CONTROL ....................................................................................................... 19

3.1 Control Registers Map ................................................................................................................................. 19

3.2 Register Descriptions ................................................................................................................................... 21

4.0 ELECTRICAL SPECIFICATIONS ........................................................................................ 41

4.1 Absolute Maximum Ratings ........................................................................................................................ 41

4.2 Recommended Operating Conditions .......................................................................................................... 41

4.3 Electrical Characteristics ............................................................................................................................. 42

4.4 Digital Inputs / Outputs DC Specifications.................................................................................................. 42

4.5 Digital Inputs / Outputs AC Specifications................................................................................................. 43

4.6 TMDS Output Specification ........................................................................................................................ 43

5.0 PACKAGE DIMENSIONS ................................................................................................... 44

6.0 REVISION HISTORY ......................................................................................................... 45

CHRONTEL CH7033B

201-1000-024 Rev1.32 04/11/2016 5

FIGURES AND TABLES

LIST OF FIGURES

Figure 1: Functional Block Diagram ............................................................................................................................. 3

Figure 2: 88 pin QFN Package (Top View) ................................................................................................................... 6

Figure 3: Clock and Data Input Timing in 3x Multiplexed Mode ............................................................................... 10

Figure 4: SDR and DDR Input Data Formats .............................................................................................................. 10

Figure 5: Horizontal Input Timing............................................................................................................................... 11

Figure 6: Vertical Input Timing ................................................................................................................................... 11

Figure 7: 80/86 MPU Interface Timing ....................................................................................................................... 11

Figure 8: SPDIF interface format ................................................................................................................................ 13

Figure 9: I2S interface format ...................................................................................................................................... 14

Figure 10: 88 Pin QFN Package (10 x 10 mm) ........................................................................................................... 44

LIST OF TABLES

Table 1: Pin Name Descriptions (QFN88 Package) ...................................................................................................... 7

Table 2: Input data format .......................................................................................................................................... 12

Table 3: Supported HDTV standards........................................................................................................................... 14

Table 4: Composite sync type ...................................................................................................................................... 14

Table 5: Video DAC Configurations for CH7033B .................................................................................................... 15

Table 6: video formats the CH7033B supports........................................................................................................... 16

Table 7: DVI output formats the CH7033B supports .................................................................................................. 16

Table 8: Popular panel size .......................................................................................................................................... 17

Table 9: Test Pattern Selection .................................................................................................................................... 17

Table 10: Serial Port Register Map ............................................................................................................................. 19

Table 11: SYNC SWAP .............................................................................................................................................. 29

Table 12: VGA Output format ..................................................................................................................................... 30

Table 13: HDTV output format ................................................................................................................................... 30

Table 14: Video DAC Configurations for CH7033 ..................................................................................................... 34

Table 15: TEST PATTERN......................................................................................................................................... 35

Table 16: TMDS output specification ......................................................................................................................... 43