Hardware and Software
Interrupt System
T TO
Technical Training
Organization
HWI
Fast response to
interrupts
Minimal context switching
High priority for CPU
Limited number of HWI
possible
SWI
Latency in response time
Context switch performed
Selectable priority levels
Execution managed by
scheduler
DSP/BIOS provides for HWI and SWI management
DSP/BIOS allows the HWI to post an SWI to the ready queue
Execution flow for flexible real-time systems:
INT ! Hard R/T Process Post SWI Cleanup, RETURN
Continue Soft R/T Processing ...
SWI Ready
HWI
SWI
{
*buf++ = *SPRR;
count--;
if (count = = 0) {
SWI_post(&swiFir);
count = COUNT;
buf = &buf2;
}
}
5
第 4 页 / 共 49 页