I2C Controller Reference Design
from Altera Corporation
Overview
The I2C Controller was designed for the MC68307 uC, provides a
simplified interface to industry-standard I2C protocol. The I2C Controller
is available in VHDL and is optimized for the Altera
®
APEX™, Stratix
®
, and Cyclone™ device families.
All of the register addresses are defined as constants in the VHDL source files and can be easily
customized for customer use. The MBASE address is defined as a generic and can also be easily
changed and customized for customer use. In addition, this design outputs the MCF signal on a pin
which can be used by the uC as a quick indication that the I2C transfer is complete.
This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges
on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise
effects which can cause improper clocking of registers within the Stratix FPGA. If the loading of the SCL
signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as
Schmitt Triggers will be required to interface to the FPGA.
Please also note that this design has been verified through simulations, but not on actual hardware.
Performance
Table 1 shows the performance results for the I2C Controller, which were generated with Quartus
®
II
software v4.2.
Table 1: Performance
Device Internal f
MAX
(MHz) LEs
APEX 20KE EP20K60EFC144-1X 175 246
APEX II EP2A15B724C7 240 246
Stratix EP1S10F780C5 308 200
Cyclone EP1C6Q240C6 300 209
Demonstrated Altera Technology
