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Tiva

™

TM4C129XNCZAD Microcontroller

DATA SHEET

Texas Instruments Incorporated

DS-TM4C129XNCZAD-15863.2743

SPMS444B

TEXAS INSTRUMENTS-PRODUCTION DATA

registered trademarks and Cortex is a trademark of ARM Limited. All other trademarks are the property of others.

PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standard

warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor

products and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated

108 Wild Basin, Suite 350

Austin, TX 78746

http://www.ti.com/tm4c

http://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

WARNING – EXPORT NOTICE: Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data

(as dened by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other

applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination

to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.

Department of Commerce and other competent Government authorities to the extent required by those laws.

According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations

of dual-use goods in force in the origin and exporting countries, this technology is classied as follows:

■ US ECCN: EAR99

■ EU ECCN: EAR99

And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries.

June 18, 20142

Texas Instruments-Production Data

Table of Contents

Revision History ............................................................................................................................. 53

About This Document .................................................................................................................... 56

Audience .............................................................................................................................................. 56

About This Manual ................................................................................................................................ 56

Related Documents ............................................................................................................................... 56

Documentation Conventions .................................................................................................................. 57

1 Architectural Overview .......................................................................................... 59

1.1 Tiva™ C Series Overview .............................................................................................. 59

1.2 TM4C129XNCZAD Microcontroller Overview .................................................................. 60

1.3 TM4C129XNCZAD Microcontroller Features ................................................................... 63

1.3.1 ARM Cortex-M4F Processor Core .................................................................................. 63

1.3.2 On-Chip Memory ........................................................................................................... 65

1.3.3 External Peripheral Interface ......................................................................................... 67

1.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 69

1.3.5 Advanced Encryption Standard (AES) Accelerator .......................................................... 69

1.3.6 Data Encryption Standard (DES) Accelerator ................................................................. 70

1.3.7 Secure Hash Algorithm / Message Digest Algorithm (SHA/MD5) ..................................... 70

1.3.8 Serial Communications Peripherals ................................................................................ 71

1.3.9 System Integration ........................................................................................................ 77

1.3.10 Advanced Motion Control ............................................................................................... 85

1.3.11 Analog .......................................................................................................................... 87

1.3.12 JTAG and ARM Serial Wire Debug ................................................................................ 88

1.3.13 Packaging and Temperature .......................................................................................... 89

1.4 TM4C129XNCZAD Microcontroller Hardware Details ...................................................... 89

1.5 Kits .............................................................................................................................. 89

1.6 Support Information ....................................................................................................... 90

2 The Cortex-M4F Processor ................................................................................... 91

2.1 Block Diagram .............................................................................................................. 92

2.2 Overview ...................................................................................................................... 93

2.2.1 System-Level Interface .................................................................................................. 93

2.2.2 Integrated Configurable Debug ...................................................................................... 93

2.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 94

2.2.4 Cortex-M4F System Component Details ......................................................................... 94

2.3 Programming Model ...................................................................................................... 95

2.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 95

2.3.2 Stacks .......................................................................................................................... 96

2.3.3 Register Map ................................................................................................................ 96

2.3.4 Register Descriptions .................................................................................................... 98

2.3.5 Exceptions and Interrupts ............................................................................................ 114

2.3.6 Data Types ................................................................................................................. 114

2.4 Memory Model ............................................................................................................ 114

2.4.1 Memory Regions, Types and Attributes ......................................................................... 118

2.4.2 Memory System Ordering of Memory Accesses ............................................................ 118

2.4.3 Behavior of Memory Accesses ..................................................................................... 118

2.4.4 Software Ordering of Memory Accesses ....................................................................... 119

3June 18, 2014

Texas Instruments-Production Data

Tiva

™

TM4C129XNCZAD Microcontroller

2.4.5 Bit-Banding ................................................................................................................. 120

2.4.6 Data Storage .............................................................................................................. 122

2.4.7 Synchronization Primitives ........................................................................................... 123

2.5 Exception Model ......................................................................................................... 124

2.5.1 Exception States ......................................................................................................... 125

2.5.2 Exception Types .......................................................................................................... 125

2.5.3 Exception Handlers ..................................................................................................... 130

2.5.4 Vector Table ................................................................................................................ 130

2.5.5 Exception Priorities ...................................................................................................... 131

2.5.6 Interrupt Priority Grouping ............................................................................................ 132

2.5.7 Exception Entry and Return ......................................................................................... 132

2.6 Fault Handling ............................................................................................................. 135

2.6.1 Fault Types ................................................................................................................. 136

2.6.2 Fault Escalation and Hard Faults .................................................................................. 136

2.6.3 Fault Status Registers and Fault Address Registers ...................................................... 137

2.6.4 Lockup ....................................................................................................................... 137

2.7 Power Management .................................................................................................... 138

2.7.1 Entering Sleep Modes ................................................................................................. 138

2.7.2 Wake Up from Sleep Mode .......................................................................................... 138

2.8 Instruction Set Summary .............................................................................................. 139

3 Cortex-M4 Peripherals ......................................................................................... 146

3.1 Functional Description ................................................................................................. 146

3.1.1 System Timer (SysTick) ............................................................................................... 147

3.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 148

3.1.3 System Control Block (SCB) ........................................................................................ 149

3.1.4 Memory Protection Unit (MPU) ..................................................................................... 149

3.1.5 Floating-Point Unit (FPU) ............................................................................................. 154

3.2 Register Map .............................................................................................................. 158

3.3 System Timer (SysTick) Register Descriptions .............................................................. 161

3.4 NVIC Register Descriptions .......................................................................................... 165

3.5 System Control Block (SCB) Register Descriptions ........................................................ 175

3.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 204

3.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 213

4 JTAG Interface ...................................................................................................... 219

4.1 Block Diagram ............................................................................................................ 220

4.2 Signal Description ....................................................................................................... 220

4.3 Functional Description ................................................................................................. 221

4.3.1 JTAG Interface Pins ..................................................................................................... 221

4.3.2 JTAG TAP Controller ................................................................................................... 223

4.3.3 Shift Registers ............................................................................................................ 224

4.3.4 Operational Considerations .......................................................................................... 224

4.4 Initialization and Configuration ..................................................................................... 227

4.5 Register Descriptions .................................................................................................. 227

4.5.1 Instruction Register (IR) ............................................................................................... 228

4.5.2 Data Registers ............................................................................................................ 229

5 System Control ..................................................................................................... 232

5.1 Signal Description ....................................................................................................... 232

5.2 Functional Description ................................................................................................. 232

June 18, 20144

Texas Instruments-Production Data

Table of Contents

5.2.1 Device Identification .................................................................................................... 233

5.2.2 Reset Control .............................................................................................................. 233

5.2.3 Non-Maskable Interrupt ............................................................................................... 240

5.2.4 Power Control ............................................................................................................. 241

5.2.5 Clock Control .............................................................................................................. 242

5.2.6 System Control ........................................................................................................... 252

5.3 Initialization and Configuration ..................................................................................... 258

5.4 Register Map .............................................................................................................. 260

5.5 System Control Register Descriptions (System Control Offset) ....................................... 267

5.6 Cryptographic System Control Register Description (CCM Offset) .................................. 554

6 Processor Support and Exception Module ........................................................ 556

6.1 Functional Description ................................................................................................. 556

6.2 Register Map .............................................................................................................. 556

6.3 Register Descriptions .................................................................................................. 556

7 Hibernation Module .............................................................................................. 564

7.1 Block Diagram ............................................................................................................ 566

7.2 Signal Description ....................................................................................................... 566

7.3 Functional Description ................................................................................................. 567

7.3.1 Register Access Timing ............................................................................................... 568

7.3.2 Hibernation Clock Source ............................................................................................ 568

7.3.3 System Implementation ............................................................................................... 571

7.3.4 Battery Management ................................................................................................... 572

7.3.5 Real-Time Clock .......................................................................................................... 572

7.3.6 Tamper ....................................................................................................................... 575

7.3.7 Battery-Backed Memory .............................................................................................. 578

7.3.8 Power Control Using HIB ............................................................................................. 578

7.3.9 Power Control Using VDD3ON Mode ........................................................................... 579

7.3.10 Initiating Hibernate ...................................................................................................... 579

7.3.11 Waking from Hibernate ................................................................................................ 579

7.3.12 Arbitrary Power Removal ............................................................................................. 580

7.3.13 Interrupts and Status ................................................................................................... 581

7.4 Initialization and Configuration ..................................................................................... 581

7.4.1 Initialization ................................................................................................................. 581

7.4.2 RTC Match Functionality (No Hibernation) .................................................................... 582

7.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 582

7.4.4 External Wake-Up from Hibernation .............................................................................. 583

7.4.5 RTC or External Wake-Up from Hibernation .................................................................. 584

7.4.6 Tamper Initialization ..................................................................................................... 584

7.5 Register Map .............................................................................................................. 584

7.6 Register Descriptions .................................................................................................. 586

8 Internal Memory ................................................................................................... 633

8.1 Block Diagram ............................................................................................................ 633

8.2 Functional Description ................................................................................................. 635

8.2.1 SRAM ........................................................................................................................ 635

8.2.2 ROM .......................................................................................................................... 635

8.2.3 Flash Memory ............................................................................................................. 637

8.2.4 EEPROM .................................................................................................................... 648

8.2.5 Bus Matrix Memory Accesses ...................................................................................... 654

5June 18, 2014

Texas Instruments-Production Data

Tiva

™

TM4C129XNCZAD Microcontroller

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