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This is the Title of the Book, eMatter Edition

302

Chapter 12

CHAPTER 12

PCI Drivers

While Chapter 9 introduced the lowest levels of hardware control, this chapter pro-

vides an overview of the higher-level bus architectures. A bus is made up of both an

electrical interface and a programming interface. In this chapter, we deal with the

programming interface.

This chapter covers a number of bus architectures. However, the primary focus is on

the kernel functions that access Peripheral Component Interconnect (PCI) peripher-

als, because these days the PCI bus is the most commonly used peripheral bus on

desktops and bigger computers. The bus is the one that is best supported by the ker-

nel. ISA is still common for electronic hobbyists and is described later, although it is

pretty much a bare-metal kind of bus, and there isn’t much to say in addition to

what is covered in Chapters 9 and 10.

The PCI Interface

Although many computer users think of PCI as a way of laying out electrical wires, it

is actually a complete set of specifications defining how different parts of a computer

should interact.

The PCI specification covers most issues related to computer interfaces. We are not

going to cover it all here; in this section, we are mainly concerned with how a PCI

driver can find its hardware and gain access to it. The probing techniques discussed

in the sections “Module Parameters” in Chapter 2 and “Autodetecting the IRQ

Number” in Chapter 10 can be used with PCI devices, but the specification offers an

alternative that is preferable to probing.

The PCI architecture was designed as a replacement for the ISA standard, with three

main goals: to get better performance when transferring data between the computer

and its peripherals, to be as platform independent as possible, and to simplify add-

ing and removing peripherals to the system.

,ch12.1659 Page 302 Friday, January 21, 2005 3:08 PM

This is the Title of the Book, eMatter Edition

The PCI Interface

303

The PCI bus achieves better performance by using a higher clock rate than ISA; its

clock runs at 25 or 33 MHz (its actual rate being a factor of the system clock), and

66-MHz and even 133-MHz implementations have recently been deployed as well.

Moreover, it is equipped with a 32-bit data bus, and a 64-bit extension has been

included in the specification. Platform independence is often a goal in the design of a

computer bus, and it’s an especially important feature of PCI, because the PC world

has always been dominated by processor-specific interface standards. PCI is cur-

rently used extensively on IA-32, Alpha, PowerPC, SPARC64, and IA-64 systems,

and some other platforms as well.

What is most relevant to the driver writer, however, is PCI’s support for autodetec-

tion of interface boards. PCI devices are jumperless (unlike most older peripherals)

and are automatically configured at boot time. Then, the device driver must be able

to access configuration information in the device in order to complete initialization.

This happens without the need to perform any probing.

PCI Addressing

Each PCI peripheral is identified by a bus number, a device number, and a function

number. The PCI specification permits a single system to host up to 256 buses, but

because 256 buses are not sufficient for many large systems, Linux now supports PCI

domains. Each PCI domain can host up to 256 buses. Each bus hosts up to 32

devices, and each device can be a multifunction board (such as an audio device with

an accompanying CD-ROM drive) with a maximum of eight functions. Therefore,

each function can be identified at hardware level by a 16-bit address, or key. Device

drivers written for Linux, though, don’t need to deal with those binary addresses,

because they use a specific data structure, called

pci_dev, to act on the devices.

Most recent workstations feature at least two PCI buses. Plugging more than one bus

in a single system is accomplished by means of bridges, special-purpose PCI peripher-

als whose task is joining two buses. The overall layout of a PCI system is a tree where

each bus is connected to an upper-layer bus, up to bus 0 at the root of the tree. The

CardBus PC-card system is also connected to the PCI system via bridges. A typical

PCI system is represented in Figure 12-1, where the various bridges are highlighted.

The 16-bit hardware addresses associated with PCI peripherals, although mostly hid-

den in the

struct pci_dev object, are still visible occasionally, especially when lists of

devices are being used. One such situation is the output of lspci (part of the pciutils

package, available with most distributions) and the layout of information in /proc/pci

and /proc/bus/pci. The sysfs representation of PCI devices also shows this addressing

scheme, with the addition of the PCI domain information.

When the hardware

address is displayed, it can be shown as two values (an 8-bit bus number and an 8-bit

* Some architectures also display the PCI domain information in the /proc/pci and /proc/bus/pci files.

,ch12.1659 Page 303 Friday, January 21, 2005 3:08 PM

This is the Title of the Book, eMatter Edition

The PCI Interface

305

0038

0048

0049

004a

0060

0078

0080

0090

0098

00a0

$ tree /sys/bus/pci/devices/

/sys/bus/pci/devices/

|-- 0000:00:00.0 -> ../../../devices/pci0000:00/0000:00:00.0

|-- 0000:00:00.1 -> ../../../devices/pci0000:00/0000:00:00.1

|-- 0000:00:00.2 -> ../../../devices/pci0000:00/0000:00:00.2

|-- 0000:00:02.0 -> ../../../devices/pci0000:00/0000:00:02.0

|-- 0000:00:04.0 -> ../../../devices/pci0000:00/0000:00:04.0

|-- 0000:00:06.0 -> ../../../devices/pci0000:00/0000:00:06.0

|-- 0000:00:07.0 -> ../../../devices/pci0000:00/0000:00:07.0

|-- 0000:00:09.0 -> ../../../devices/pci0000:00/0000:00:09.0

|-- 0000:00:09.1 -> ../../../devices/pci0000:00/0000:00:09.1

|-- 0000:00:09.2 -> ../../../devices/pci0000:00/0000:00:09.2

|-- 0000:00:0c.0 -> ../../../devices/pci0000:00/0000:00:0c.0

|-- 0000:00:0f.0 -> ../../../devices/pci0000:00/0000:00:0f.0

|-- 0000:00:10.0 -> ../../../devices/pci0000:00/0000:00:10.0

|-- 0000:00:12.0 -> ../../../devices/pci0000:00/0000:00:12.0

|-- 0000:00:13.0 -> ../../../devices/pci0000:00/0000:00:13.0

`-- 0000:00:14.0 -> ../../../devices/pci0000:00/0000:00:14.0

All three lists of devices are sorted in the same order, since lspci uses the /proc files as

its source of information. Taking the VGA video controller as an example,

0x00a0

means 0000:00:14.0 when split into domain (16 bits), bus (8 bits), device (5 bits) and

function (3 bits).

The hardware circuitry of each peripheral board answers queries pertaining to three

address spaces: memory locations, I/O ports, and configuration registers. The first

two address spaces are shared by all the devices on the same PCI bus (i.e., when you

access a memory location, all the devices on that PCI bus see the bus cycle at the

same time). The configuration space, on the other hand, exploits geographical

addressing. Configuration queries address only one slot at a time, so they never collide.

As far as the driver is concerned, memory and I/O regions are accessed in the usual

ways via inb, readb, and so forth. Configuration transactions, on the other hand, are

performed by calling specific kernel functions to access configuration registers. With

regard to interrupts, every PCI slot has four interrupt pins, and each device function

can use one of them without being concerned about how those pins are routed to the

CPU. Such routing is the responsibility of the computer platform and is imple-

mented outside of the PCI bus. Since the PCI specification requires interrupt lines to

be shareable, even a processor with a limited number of IRQ lines, such as the x86,

can host many PCI interface boards (each with four interrupt pins).

,ch12.1659 Page 305 Friday, January 21, 2005 3:08 PM

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