PI7C9X2G404SVPCI Express Gen2 Packet Switch Application Note 0.2...
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www.diodes.com 12/4/2019
PI7C9X2G404SV / PI7C9X2G304SV / PI7C9X2G404EV / PI7C9X2G304EV
PCI Express® Gen2 Packet Switch Guidelines
1. Introduction
This application note provides a concise and practical
guide for the board designers to easily incorporate the
Pericom PCI Express Gen2 Packet Switches in their
designs. This document includes design outlines,
layout cautions and application reminders, which can
help the designers to achieve optimal performance in
their systems.
2. Differential Impedance
For microstrip traces, an impedance target of 85Ω with
a max 10% impedance tolerance is desired for 6-layer
printed circuit board stackups.
For stripline traces, an impedance target of 85Ω with a
max 10% impedance tolerance is desired for 6-layer
printed circuit board stackups.
3. Single-Ended Impedance
For microstrip traces, an impedance target of 50Ω with
a max 10% impedance tolerance is desired for 6-layer
printed circuit board stackups.
For stripline traces, an impedance target of 50Ω with a
max 10% impedance tolerance is desired for 6-layer
printed circuit board stackups.
4. Differential Pair Length Restrictions
Trace routing lengths from a chipset to a connector
(microstrip and stripline) are limited to 10 inches.
5. Layout Guidelines for PI7C9X2Gx04EV
5.1. Trace Width And Clearance
1. The trace length miss-matching shall be less
than 5 mils for the “+” and “–“ traces in the same
pairs
2. More pair-to-pair spacing for minimal crosstalk
3. Target differential Zo of 85ohm ±10%
5.2. The PCB Layers Stackup
1. Use FR4.
2. Use standard 4 to 8 layers stack-up with 0.062
inch thick PCB.
3. For micro-strip lines, using ½ OZ Cu plated is ok.
4. For strip-lines in 6 plus players, using 1 OZ Cu
is better.
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