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Document Number: MD00743

Revision 3.02

March 21, 2011

MIPS Technologies, Inc.

955 East Arques Avenue

Sunnyvale, CA 94085-4521

MIPS® Architecture For Programmers

Volume I-B: Introduction to the

microMIPS64® Architecture

MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS64® Architecture, Revision 3.02

Template: nB1.03, Built with tags: 2B ARCH FPU_PS FPU_PSandARCH MIPS64

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MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS64® Architecture, Revision 3.02 3

Contents

Chapter 1: About This Book ..................................................................................................................9

1.1: Typographical Conventions......................................................................................................................... 9

1.1.1: Italic Text............................................................................................................................................ 9

1.1.2: Bold Text.......................................................................................................................................... 10

1.1.3: Courier Text ..................................................................................................................................... 10

1.2: UNPREDICTABLE and UNDEFINED ....................................................................................................... 10

1.2.1: UNPREDICTABLE........................................................................................................................... 10

1.2.2: UNDEFINED .................................................................................................................................... 11

1.2.3: UNSTABLE ...................................................................................................................................... 11

1.3: Special Symbols in Pseudocode Notation................................................................................................. 11

1.4: For More Information................................................................................................................................. 14

Chapter 2: The MIPS Architecture: An Introduction..........................................................................15

2.1: MIPS Instruction Set Overview.................................................................................................................. 15

2.1.1: Historical Perspective....................................................................................................................... 15

2.1.2: Architectural Evolution ..................................................................................................................... 16

2.1.3: Architectural Changes Relative to the MIPS I through MIPS V Architectures.................................. 19

2.2: Compliance and Subsetting....................................................................................................................... 19

2.3: Components of the MIPS Architecture ...................................................................................................... 21

2.3.1: MIPS Instruction Set Architecture (ISA)........................................................................................... 21

2.3.2: MIPS Privileged Resource Architecture (PRA) ................................................................................ 22

2.3.3: MIPS Application Specific Extensions (ASEs) ................................................................................. 22

2.3.4: MIPS User Defined Instructions (UDIs)............................................................................................ 22

2.4: Architecture Versus Implementation.......................................................................................................... 22

2.5: Relationship between the MIPSr3 Architectures ....................................................................................... 22

2.6: Pipeline Architecture.................................................................................................................................. 24

2.6.1: Pipeline Stages and Execution Rates.............................................................................................. 24

2.6.2: Parallel Pipeline ............................................................................................................................... 25

2.6.3: Superpipeline ................................................................................................................................... 25

2.6.4: Superscalar Pipeline ........................................................................................................................ 26

2.7: Load/Store Architecture............................................................................................................................. 26

2.8: Programming Model .................................................................................................................................. 27

2.8.1: CPU Data Formats........................................................................................................................... 27

2.8.2: FPU Data Formats ........................................................................................................................... 27

2.8.3: Coprocessors (CP0-CP3) ................................................................................................................ 28

2.8.4: CPU Registers ................................................................................................................................. 28

2.8.5: FPU Registers.................................................................................................................................. 30

2.8.6: Byte Ordering and Endianness ........................................................................................................ 35

2.8.7: Memory Access Types..................................................................................................................... 37

2.8.8: Implementation-Specific Access Types ........................................................................................... 38

2.8.9: Cacheability and Coherency Attributes and Access Types.............................................................. 38

2.8.10: Mixing Access Types ..................................................................................................................... 38

2.8.11: Instruction Fetches......................................................................................................................... 39

Chapter 3: Application Specific Extensions ......................................................................................45

3.1: Description of ASEs................................................................................................................................... 45

3.2: List of Application Specific Instructions ..................................................................................................... 46

4 MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS64® Architecture, Revision 3.02

3.2.1: The MDMX™ Application Specific Extension to the microMIPS64 Architectures............................ 46

3.2.2: The MIPS-3D® Application Specific Extension to the microMIPS Architecture............................... 46

3.2.3: The SmartMIPS® Application Specific Extension to the microMIPS32 Architecture ....................... 46

3.2.4: The MIPS® DSP Application Specific Extension to the MIPS Architecture ..................................... 46

3.2.5: The MIPS® MT Application Specific Extension to the MIPS Architecture ....................................... 46

3.2.6: The MIPS® MCU Application Specific Extension to the MIPS Architecture .................................... 47

Chapter 4: Overview of the CPU Instruction Set ...............................................................................49

4.1: CPU Instructions, Grouped By Function.................................................................................................... 49

4.1.1: CPU Load and Store Instructions..................................................................................................... 49

4.1.2: Computational Instructions............................................................................................................... 53

4.1.3: Jump and Branch Instructions.......................................................................................................... 58

4.1.4: Miscellaneous Instructions............................................................................................................... 61

4.1.5: Coprocessor Instructions ................................................................................................................. 64

4.1.6: CPU Instruction Restrictions ............................................................................................................ 65

Chapter 5: Overview of the FPU Instruction Set................................................................................67

5.1: Binary Compatibility................................................................................................................................... 67

5.2: Enabling the Floating Point Coprocessor .................................................................................................. 68

5.3: IEEE Standard 754.................................................................................................................................... 68

5.4: FPU Data Types........................................................................................................................................ 68

5.4.1: Floating Point Formats..................................................................................................................... 68

5.4.2: Fixed Point Formats......................................................................................................................... 72

5.5: Floating Point Register Types ................................................................................................................... 73

5.5.1: FPU Register Models....................................................................................................................... 73

5.5.2: Binary Data Transfers (32-Bit and 64-Bit)........................................................................................ 73

5.5.3: FPRs and Formatted Operand Layout............................................................................................. 74

5.6: Floating Point Control Registers (FCRs) ................................................................................................... 75

5.6.1: Floating Point Implementation Register (FIR, CP1 Control Register 0)........................................... 75

5.6.2: Floating Point Control and Status Register (FCSR, CP1 Control Register 31)................................ 77

5.6.3: Floating Point Condition Codes Register (FCCR, CP1 Control Register 25)................................... 80

5.6.4: Floating Point Exceptions Register (FEXR, CP1 Control Register 26) ............................................ 80

5.6.5: Floating Point Enables Register (FENR, CP1 Control Register 28)................................................. 81

5.7: Formats of Values Used in FP Registers .................................................................................................. 82

5.8: FPU Exceptions......................................................................................................................................... 82

5.8.1: Exception Conditions ....................................................................................................................... 83

5.9: FPU Instructions........................................................................................................................................ 85

5.9.1: Data Transfer Instructions................................................................................................................ 86

5.9.2: Arithmetic Instructions...................................................................................................................... 87

5.9.3: Conversion Instructions.................................................................................................................... 89

5.9.4: Formatted Operand-Value Move Instructions .................................................................................. 90

5.9.5: Conditional Branch Instructions ....................................................................................................... 91

5.9.6: Miscellaneous Instructions............................................................................................................... 91

5.10: Valid Operands for FPU Instructions....................................................................................................... 92

5.11: FPU Instruction Formats.......................................................................................................................... 94

Appendix B: Revision History .............................................................................................................95

MIPS® Architecture For Programmers Volume I-B: Introduction to the microMIPS64® Architecture, Revision 3.02 5

Figures

Figure 2-1: MIPS Architectures............................................................................................................................... 16

Figure 2-2: Relationship of the Binary Representations of MIPSr3 Architectures................................................... 23

Figure 2-3: Relationships of the Assembler Source Code Representations of the MIPSr3 Architectures.............. 24

Figure 2-4: One-Deep Single-Completion Instruction Pipeline ............................................................................... 25

Figure 2-5: Four-Deep Single-Completion Pipeline ................................................................................................ 25

Figure 2-6: Four-Deep Superpipeline...................................................................................................................... 26

Figure 2-7: Four-Way Superscalar Pipeline............................................................................................................ 26

Figure 2-8: CPU Registers...................................................................................................................................... 30

Figure 2-9: FPU Registers for a 32-bit FPU............................................................................................................ 32

Figure 2-10: FPU Registers for a 64-bit FPU if Status

is 1 ................................................................................ 33

Figure 2-11: FPU Registers for a 64-bit FPU if Status

is 0 ................................................................................. 34

Figure 2-12: Big-Endian Byte Ordering................................................................................................................... 35

Figure 2-13: Little-Endian Byte Ordering................................................................................................................. 35

Figure 2-14: Big-Endian Data in Doubleword Format ............................................................................................. 36

Figure 2-15: Little-Endian Data in Doubleword Format........................................................................................... 36

Figure 2-16: Big-Endian Misaligned Word Addressing ........................................................................................... 37

Figure 2-17: Little-Endian Misaligned Word Addressing......................................................................................... 37

Figure 2-18: Three instructions placed in a 64-bit wide, little-endian memory........................................................ 39

Figure 2-19: Three instructions placed in a 64-bit wide, big-endian memory.......................................................... 40

Figure 3-1: microMIPS ISAs and ASEs................................................................................................................... 45

Figure 5-1: Single-Precisions Floating Point Format (S)......................................................................................... 69

Figure 5-2: Double-Precisions Floating Point Format (D) ....................................................................................... 69

Figure 5-3: Paired Single Floating Point Format (PS)............................................................................................. 70

Figure 5-4: Word Fixed Point Format (W)............................................................................................................... 72

Figure 5-5: Longword Fixed Point Format (L) ......................................................................................................... 72

Figure 5-6: FPU Word Load and Move-to Operations ........................................................................................... 74

Figure 5-7: FPU Doubleword Load and Move-to Operations.................................................................................. 74

Figure 5-8: Single Floating Point or Word Fixed Point Operand in an FPR ........................................................... 74

Figure 5-9: Double Floating Point or Longword Fixed Point Operand in an FPR ................................................... 75

Figure 5-10: Paired-Single Floating Point Operand in an FPR ............................................................................... 75

Figure 5-11: FIR Register Format .......................................................................................................................... 75

Figure 5-12: FCSR Register Format ...................................................................................................................... 78

Figure 5-13: FCCR Register Format ...................................................................................................................... 80

Figure 5-14: FEXR Register Format ...................................................................................................................... 81

Figure 5-15: FENR Register Format ...................................................................................................................... 81