8051在CycloneFPGANios上实现的全部源代码资源-CSDN文库

共136个文件

vhd：63个

exe：6个

rpt：5个

Cyclone

FPGA

Nios

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8051在Cyclone FPGA Nios上实现的全部源代码（136个子文件）

rpt_mc8051_top.areasrr 36KB

ramload.asm 5KB

mc8051_top_.cdf 321B

SERLCD.CPP 6KB

SERLOAD.CPP 5KB

SERSHAKE.CPP 4KB

mc8051_top_.done 26B

mc8051_top_.fit.eqn 1.28MB

mc8051_top_.map.eqn 1.14MB

SERLOAD211.EXE 35KB

SERLOAD243.EXE 35KB

SERLOAD147.EXE 35KB

SERLOAD179.EXE 35KB

SERLCD.EXE 33KB

SERSHAKE.EXE 32KB

mc8051_top.fse 0B

RAMLOAD.hex 2KB

autobaud.hex 586B

demo.hex 222B

cmp_state.ini 2B

ramload.lnp 46B

ramload.LST 22KB

ramload.M51 16KB

ramload.OBJ 4KB

ramload.Opt 1KB

mc8051_cyclone_nios_designflow.pdf 194KB

mc8051_top_.pin 47KB

mc8051_top.plg 1020B

ramload.plg 162B

mc8051_top_.pof 512KB

mc8051_core.prd 329B

mc8051_core.prj 3KB

mc8051_top__assignment_defaults.qdf 29KB

mc8051_top_.qpf 2KB

mc8051_top_.qsf 13KB

mc8051_top_.qsf~ 13KB

mc8051_top_.qws 269B

ramload 3KB

.recordref 0B

mc8051_top_.fit.rpt 1.1MB

mc8051_top_.tan.rpt 172KB

mc8051_top_.map.rpt 41KB

mc8051_top_.asm.rpt 9KB

mc8051_top_.flow.rpt 4KB

mc8051_core.sdc 2KB

mc8051_top_.sof 425KB

mc8051_top_hit.sof 425KB

mc8051_top.srd 1.5MB

mc8051_top.srm 1.63MB

mc8051_top.srr 174KB

mc8051_top.srs 394KB

mc8051_top_.tan.summary 2KB

mc8051_top_.fit.summary 412B

mc8051_top_.map.summary 347B

mc8051_top.sxr 237KB

mc8051_top.tcl 10KB

mc8051_top_rm.tcl 2KB

mc8051_top_cons.tcl 179B

mc8051_top.tlg 17KB

LGPL.TXT 26KB

version.txt 586B

mc8051_top__description.txt 2B

ramload.Uv2 2KB

control_fsm_rtl.vhd 98KB

mc8051_siu_rtl.vhd 50KB

control_mem_rtl.vhd 47KB

mc8051_p.vhd 44KB

mc8051_tmrctr_rtl.vhd 31KB

alumux_rtl.vhd 18KB

mc8051_control_struc.vhd 11KB

mc8051_core_struc.vhd 11KB

control_mem_.vhd 10KB

mc8051_top_struc.vhd 10KB

mc8051_pram.vhd 10KB

cyclonepll.vhd 10KB

mc8051_alu_struc.vhd 8KB

mc8051_control_.vhd 8KB

mc8051_ramx.vhd 8KB

alucore_rtl.vhd 7KB

mc8051_ram.vhd 7KB

dcml_adjust_rtl.vhd 7KB

mc8051_core_.vhd 7KB

addsub_ovcy_rtl.vhd 7KB

alumux_.vhd 7KB

mc8051_rom.vhd 6KB

control_fsm_.vhd 6KB

mc8051_top_.vhd 6KB

addsub_core_struc.vhd 6KB

comb_divider_rtl.vhd 6KB

mc8051_tmrctr_.vhd 5KB

mc8051_alu_.vhd 5KB

mc8051_siu_.vhd 5KB

mc8051_alu_struc_cfg.vhd 5KB

addsub_cy_rtl.vhd 5KB

alucore_.vhd 5KB

dcml_adjust_.vhd 5KB

addsub_core_.vhd 5KB

addsub_ovcy_.vhd 5KB

addsub_core_struc_cfg.vhd 5KB

共 136 条

8051 IP Core

Bootstrap Demo Design - User Guide

Erfolg folgt Erfahrung

Implementing the MC8051 IP Core On A Cyclone Nios Board

First of all it is necessary to exchange the simulation models of all the memory blocks with

real memory that can be found inside the target FPGA. It is also recommended to implement a

PLL to get a clock signal with a lower frequency than that of the on-board oscillator. The

VHDL code for these entities is generated by the backend tool, i.e. Quartus II 4.0 for Altera

FPGAs.

Step 1: Choose the function that should be generated.

1. After starting Quartus II, launch the Megawizard

Plug-In Manager that is located in the Tools-Menu.

2. Select the function block that

should be generated.

The PLL will be designed first.

This function can be found in the

I/O folder and is named ALTPLL.

In a second turn the memories

will be drawn. The functions for

those blocks can be found in the

folder named storage. It contains

the functions LPM_ROM for the

mc8051_rom entity and

LPM_RAM_DQ for the entity

mc8051_ram and mc8051_ramx

respectively.

3. Set the device family to Cyclone.

Then choose the language of the

HDL output file.

Finally the name of the output file

and its destination directory must

be set. It is recommended to store

all code files belonging to FPGA

functions in a directory named

generate.

8051 IP Core

Bootstrap Demo Design - User Guide

Erfolg folgt Erfahrung

When the function has been selected and the output path has been chosen, the behaviour and

the parameters of this function must be defined. This must be done for the PLL, the ROM and

the internal and external RAM.

Step 2: Define the behaviour and the parameters of the PLL.

1. Enter the input frequency for the PLL. In the case of

the NIOS Cyclone Board this frequency is 50 MHz.

The PLL operates with an internal feedback in

normal mode.

2. It is also possible to add optional inputs to the PLL.

To keep the design simple, none of the inputs are

selected.

3. If only one clock output is used,

this output is automatically set to

c0. Entering the value of the

frequency or selecting the factor

for the multiplication and the

division respectively can define

the output frequency of the PLL.

Be sure that the chosen settings

can be implemented which is

shown at the top of the window.

4. Since no other PLL outputs are selected for operation, the remaining dialogs can be

skipped. Finally all files that will be generated are shown.

Step 3: Define the behaviour and the parameters of the ROM.

1. As the ROM is a memory function, the size of the

memory and the width of the data bus have to be

defined. In the case shown at the right, the ROM is

organized 8k x 8 bit.

To meet the signals of the MC8051 design, single

clocking must be used.

2. The data output q of the ROM must not be registered

for the MC8051 design since it is not supposed to be.

As the ROM and the RAM blocks have designated

address and data busses, there is no need for a clock

enable signal.

8051 IP Core

Bootstrap Demo Design - User Guide

Erfolg folgt Erfahrung

3. The program file must be loaded into the memory.

This can be achieved by pointing to the HEX file that

contains the user program.

4. Confirm the generation of the files.

Step 4: Define the behaviour and the parameters of the internal and external RAM.

1. Enter the width of the address and data bus as shown for the ROM.

2. Select the behaviour of the input and output as shown for the ROM.

3. Let the software decide how to implement the

RAM block. If it is necessary, the RAM can be

preloaded with an additional HEX file.

4. Confirm the generation of the files.

Since the package file and the top level design refers to the simulation models for the memory

blocks, the declaration of the ports and the wiring must be updated for exchange with the

implementation models. If required the PLL must also be added to the design.

Step 5: Update the component declaration in the package file.

After all files for the implementation models have been generated, the component declaration

for the memories in the package file mc8051_p.vhd must be updated to the entity declaration

that can be found in the generated code file. For the case of the additional PLL it is also

necessary to add a new component declaration for that entity. The package file should contain

the following component declarations.

8051 IP Core

Bootstrap Demo Design - User Guide

Erfolg folgt Erfahrung

component mc8051_ram

port (address : in std_logic_vector(6 downto 0); -- address input

clock : in std_logic; -- clock input

data : in std_logic_vector(7 downto 0); -- data input

wren : in std_logic; -- write enable

q : out std_logic_vector(7 downto 0)); -- data output

end component;

component mc8051_ramx

port (address : in std_logic_vector(12 downto 0); -- address input

clock : in std_logic; -- clock input

data : in std_logic_vector(7 downto 0); -- data input

wren : in std_logic; -- write enable

q : out std_logic_vector(7 downto 0)); -- data output

end component;

component mc8051_rom

port (address : in std_logic_vector(12 downto 0); -- address input

clock : in std_logic; -- clock input

q : out std_logic_vector(7 downto 0)); -- data output

end component;

component cyclonepll

port (inclk0 : in std_logic; -- PLL input

c0 : out std_logic); -- PLL output

end component;

Step 6: Update the wiring of the top level design.

The wiring between the entities found in the top level design mc8051_top_struc.vhd also has

to be updated. If the width of the address busses of the memories differs from the 16 bit wide

busses provided by the MC8051 core, the smaller bus signals s_rom_adr_sml and

s_ramx_adr_sml have to be inserted. If the PLL should be implemented, a new clock signal

clk_pll has to be added between the PLL output and the components of the top level design.

Since the switches located on the NIOS Cyclone Board are active low, the active high reset

signal s_reset for the MC8051 core can be gained from the reset switch by an additional

inverter.

architecture struc of mc8051_top is

signal s_clk_pll : std_logic; -- core clock, PLL output

signal s_reset : std_logic; -- reset signal, active high

signal s_rom_adr_sml : std_logic_vector(12 downto 0); -- *** new

signal s_ramx_adr_sml : std_logic_vector(12 downto 0); -- *** new

begin -- architecture structural

s_rom_adr_sml <= std_logic_vector(s_rom_adr(12 downto 0));

s_ramx_adr_sml <= std_logic_vector(s_ramx_adr(12 downto 0));

s_reset <= not reset;

i_mc8051_core : mc8051_core

port map (clk => s_clk_pll, -- mc8051 core

reset => s_reset,

...

);

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内容反馈

woniu1351

2013-04-16

因为是vhdl，所以也看不懂，只有照着例子编译。不过能实现功能
由硬到软-产品经理

2012-08-28

vhdl 不好看啊

wgwang314

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