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Aurora 8B/10B v11.1

LogiCORE IP Product Guide

Vivado Design Suite

PG046 October 19, 2023

AMD Adaptive Computing is creating an environment where

employees, customers, and partners feel welcome and included.

To that end, we’re removing non-inclusive language from our

products and related collateral. We’ve launched an internal

initiative to remove language that could exclude people or

reinforce historical biases, including terms embedded in our

software and IPs. You may still find examples of non-inclusive

language in our older products as we work to make these

changes and align with evolving industry standards. Follow this

link for more information.

Aurora 8B/10B v11.1 2

PG046 October 19, 2023

Table of Contents

IP Facts

Chapter 1: Overview

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2: Product Specification

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 3: Designing with the Core

General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Serial Transceiver Reference Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Using the Scrambler/Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Using CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Hot-Plug Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Clock Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Using Little Endian Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Chapter 5: Detailed Example Design

Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Using the Vivado Design Suite Debug Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Send Feedback

Aurora 8B/10B v11.1 3

PG046 October 19, 2023

Chapter 6: Test Bench

Appendix A: Verification, Compliance, and Interoperability

Appendix B: Upgrading

Device Migration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Migrating Local Link-based Aurora Cores to the AXI4-Stream Aurora Core . . . . . . . . . . . . . . . . . . 91

Appendix C: Debugging

Finding Help with AMD Adaptive Computing Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Next Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

AXI4-Stream Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Appendix D: Generating a Wrapper File from the Transceiver Wizard

Appendix E: Handling Timing Errors

Appendix F: Additional Resources and Legal Notices

Support Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Finding Additional Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Send Feedback

Aurora 8B/10B v11.1 4

PG046 October 19, 2023

Introduction

The AMD LogiCORE™ IP Aurora 8B/10B core

supports the AMBA® protocol AXI4-Stream

user interface. The core implements the Aurora

8B/10B protocol using the high-speed serial

transceivers on AMD Zynq™ 7000 SoC, AMD

Artix™ 7, AMD Kintex™ 7 and AMD Virtex™ 7

families, AMD UltraScale™ and AMD

UltraScale+

™ families.

Features

• General-purpose data channels with throughput

range from 480 Mbps to 84.48 Gbps

• Supports up to 16 consecutively bonded 7

series GTX/GTH, UltraScale™ GTH or UltraScale+

GTH transceivers and up to four bonded GTP

transceivers

• Aurora 8B/10B protocol specification v2.3

compliant

• Low resource cost (see Resource Utilization)

• Easy-to-use AXI4-Stream based framing (or

streaming) and flow control interfaces

• Automatically initializes and maintains the

channel

• Full-duplex or simplex operation

• 16-bit additive scrambler/descrambler

• 16-bit or 32-bit Cyclic Redundancy Check (CRC)

for user data

• Hot-plug logic

• Configurable DRP/INIT clock

• Single/Differential clocking option for

GTREFCLK and core INIT_CLK

IP Facts

LogiCORE IP Facts Table

Core Specifics

Supported

Device

Family

(1)

AMD UltraScale+™

(2)

, AMD UltraScale™

(2)

AMD Zynq™ 7000,

AMD 7 Series

(3)

Supported

User Interfaces

AXI4-Stream

Resources Performance and Resource Utilization web page

Provided with Core

Design Files Register transfer level (RTL)

Example

Design

Verilog and VHDL

(2)

Test Bench Verilog and VHDL

(4)

Constraints

File

Xilinx Design Constraints (XDC)

Simulation

Model

Source HDL with SecureIP transceiver simulation

models

Supported

S/W Driver

N/A

Tested Design Flows

(5)

Design Entry AMD Vivado™ Design Suite

Simulation

For supported simulators, see the

Vivado Design Suite User Guide: Release Notes,

Installation, and Licensing.

Synthesis Vivado Synthesis

Support

Release Notes

and Known

Issues

Master Answer Record: 54367

All Vivado IP

Change Logs

Master Vivado IP Change Logs: 72775

Support web page

Notes:

1. For a complete list of supported devices and configurations, see the

Vivado IP catalog and associated FPGA data sheets.

2. For more information, see the Virtex UltraScale FPGAs Data Sheet: DC

and AC Switching Characteristics (DS893) [Ref 20], Kintex UltraScale

FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 19],

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching

Characteristics (DS922) [Ref 21], and Virtex UltraScale+ FPGAs Data

Sheet: DC and AC Switching Characteristics (DS923) [Ref 22].

3. For more information, see the 7 Series FPGAs Overview (DS180) [Ref 17]

and the UltraScale Architecture and Product Overview (DS890) [Ref 18].

4. The IP core is delivered as Verilog source code and comes with an

example design and supporting modules for simple simulation and

hardware demonstration.

5. For the supported versions of the tools, see the

Vivado Design Suite User Guide: Release Notes, Installation, and

Licensing.

Send Feedback

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