SPI串行配置加载fpga代码（HI3531DV200驱动方式）

#include <linux/module.h> #include <linux/kernel.h> #include <linux/printk.h> #include <linux/version.h> #include <linux/of_platform.h> #include <asm/io.h> #include <linux/gpio.h> #include <linux/fs.h> #include <linux/path.h> #include <linux/dcache.h> #include <linux/fdtable.h> #include<linux/delay.h> #define SYS_WRITEL(Addr, Value) ((*(volatile unsigned int *)(Addr)) = (Value)) #define FPGA_SPI_MOSI 122 //GPIO15_1 #define FPGA_SPI_CLK 123 //GPIO15_3 #define FPGA_PROG_B 125 //GPIO15_5 #define FPGA_DONE 166 //GPIO20_6 #define FPGA_INIT 167 //GPIO20_7 static void *g_reg_iocfg_base = NULL; /* ############## qosbuf ############# */ static int load_fpga(void) { int i=0, j = 0, k=0; unsigned char ucTmp = 0; struct file *fp = filp_open("/app/fpga/fpga.bin", O_RDONLY, 0); char buffer[1024] = ""; loff_t offset = 0; int len = 0; if(IS_ERR(fp)) { printk("fpga bin not exist!\n"); return -1; } SYS_WRITEL(g_reg_iocfg_base+0x0120, 0x1200); SYS_WRITEL(g_reg_iocfg_base+0x0124, 0x1200); SYS_WRITEL(g_reg_iocfg_base+0x0128, 0x1200); SYS_WRITEL(g_reg_iocfg_base+0x012C, 0x1200); SYS_WRITEL(g_reg_iocfg_base+0x01D0, 0x1200); SYS_WRITEL(g_reg_iocfg_base+0x01D4, 0x1200); gpio_request(FPGA_SPI_MOSI, "FPGA_SPI_MOSI"); gpio_request(FPGA_SPI_CLK, "FPGA_SPI_CLK"); gpio_request(FPGA_PROG_B, "FPGA_PROG_B"); gpio_request(FPGA_DONE, "FPGA_DONE"); gpio_request(FPGA_INIT, "FPGA_INIT"); gpio_direction_output(FPGA_SPI_MOSI, 1); gpio_direction_output(FPGA_SPI_CLK, 1); gpio_direction_output(FPGA_PROG_B, 1); gpio_direction_input(FPGA_DONE); gpio_direction_input(FPGA_INIT); printk("Begin Load FPGA ... \n"); while(0) //test { gpio_set_value(FPGA_PROG_B, 0); gpio_set_value(FPGA_SPI_CLK, 0); gpio_set_value(FPGA_SPI_MOSI, 0); mdelay(20); gpio_set_value(FPGA_PROG_B, 1); gpio_set_value(FPGA_SPI_CLK, 1); gpio_set_value(FPGA_SPI_MOSI, 1); mdelay(20); } gpio_set_value(FPGA_PROG_B, 1); udelay(2000); gpio_set_value(FPGA_PROG_B, 0); udelay(2000); if (0 != gpio_get_value(FPGA_INIT)) { printk("FPGA: initB singal can't turn low--0\r\n"); return -1; } gpio_set_value(FPGA_PROG_B, 1); mdelay(20); if (0 == gpio_get_value(FPGA_INIT)) { printk("FPGA: initB singal can't turn low--1\r\n"); return -1; } //按照时序加载FPGA数据文件 //flsah加载 for (i = 0; i < 10240; i++) { memset(buffer, 0, sizeof(buffer)); len = kernel_read(fp, buffer, sizeof(buffer), &offset); //printk("read cnt=%d, len=%d\n", i+1, len); if(len <=0) { printk("read fpga bin over, len=%lld\n", offset); break ; } for (k = 0; k < len; k++) { for (j = 0; j < 8; j++) { ucTmp = (buffer[k] << j) & 0x80; if(ucTmp == 0x80) ucTmp = 1; gpio_set_value(FPGA_SPI_CLK, 0); gpio_set_value(FPGA_SPI_MOSI, ucTmp); gpio_set_value(FPGA_SPI_CLK, 1); } } } udelay(1000); if (0 != gpio_get_value(FPGA_DONE)) { printk("done signal ok\r\n"); } else { printk("not done!\r\n"); } filp_close(fp, NULL); gpio_free(FPGA_SPI_MOSI); gpio_free(FPGA_SPI_CLK); gpio_free(FPGA_PROG_B); gpio_free(FPGA_DONE); gpio_free(FPGA_INIT); return 0; } static int sysconfig_init(void) { g_reg_iocfg_base = (void*)ioremap(0x17C70000, 0x10000); if (g_reg_iocfg_base == NULL) { return 1; } return 0; } static void sysconfig_exit(void) { if (g_reg_iocfg_base != NULL) { iounmap(g_reg_iocfg_base); g_reg_iocfg_base = 0; } } static int __init hi_sysconfig_init(void) { if (sysconfig_init() != 0) { goto out; } load_fpga(); out: sysconfig_exit(); return 0; } static void __exit hi_sysconfig_exit(void) { sysconfig_exit(); return; } module_init(hi_sysconfig_init); module_exit(hi_sysconfig_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Hisilicon");