PRODUCTPREVIEW
EQ50F100
www.ti.com
SNOSAB8D –OCTOBER 2004–REVISED APRIL 2005
EQ50F100 1Gbps - 6.25 Gbps Backplane Equalizer
Check for Samples: EQ50F100
1
FEATURES
• Equalize up to 20dB loss at 2.5 GHz
• 35 ps residual deterministic jitter at 5 Gbps
2
• Recovers 6.25 Gbps signals after 30" of FR4
• On-chip CML terminations
• Single 1.8V power supply
• Small 3 mm x 3 mm 6–pin leadless LLP
• Low power consumption: 85mW
package
DESCRIPTION
The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-
induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for
up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning
equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps
Ethernet Systems.
The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm
6–pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
Copyright © 2004–2005, Texas Instruments Incorporated
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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