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TMS626812B

1 048 576 BY 8-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

SMOS693A – OCTOBER 1997 – REVISED APRIL 1998

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SYNCHRONOUS

CLOCK

CYCLE TIME

ACCESS TIME

(CLOCK TO

OUTPUT)

REFRESH

TIME

INTERVAL

t

CK3

(CL

†

=3)

t

CK2

(CL=2)

t

AC3

(CL=3)

t

AC2

(CL=2)

’626812B-8 8 ns 10 ns 6 ns 6 ns 64 ms

’626812B-8A 8 ns 15 ns 6 ns 7 ns 64 ms

’626812B-10 10 ns 15 ns 7.5 ns 7.5 ns 64 ms

†

CL = CAS latency

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D

Organization

1048576 by 8 Bits by 2 Banks

D

3.3-V Power Supply (±10% Tolerance)

D

Two Banks for On-Chip Interleaving

(Gapless Accesses)

D

High Bandwidth – Up to 125-MHz Data

Rates

D

CAS Latency (CL) Programmable to

2 or 3 Cycles From Column-Address Entry

D

Burst Sequence Programmable to Serial or

Interleave

D

Burst Length Programmable to 1, 2, 4, or 8

D

Chip Select and Clock Enable for Enhanced

System Interfacing

D

Cycle-by-Cycle DQ Bus Mask Capability

D

Auto-Refresh and Self-Refresh Capabilities

D

4K Refresh (Total for Both Banks)

D

High-Speed, Low-Noise, Low-Voltage TTL

(LVTTL) Interface

D

Power-Down Mode

D

Compatible With JEDEC Standards

D

Pipeline Architecture

D

Temperature Ranges

Operating, 0°C to 70°C

Storage, – 55°C to 150°C

D

Intel PC100 Compliant (-8A, -8, and

-10 Devices)

D

Performance Ranges:

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

V

SS

DQ7

V

SSQ

DQ6

V

CCQ

DQ5

V

SSQ

DQ4

V

CCQ

NC

DQM

CLK

CKE

NC

A9

A8

A7

A6

A5

A4

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

V

CC

DQ0

V

SSQ

DQ1

V

CCQ

DQ2

V

SSQ

DQ3

V

CCQ

NC

W

CAS

RAS

CS

A11

A10

A0

A1

A2

A3

V

CC

TMS626812B

DGE PACKAGE

( TOP VIEW )

PIN NOMENCLATURE

A0–A10 Address Inputs

A0–A10 Row Addresses

A0–A8 Column Addresses (for TMS626812B)

A10 Automatic-Precharge Select

A11 Bank Select

CAS

Column-Address Strobe

CKE Clock Enable

CLK System Clock

CS

Chip Select

DQ[0:7] SDRAM Data Input/Output (TMS626812B)

DQM Data-Input/Data-Output Mask Enable

NC No External Connect

RAS Row-Address Strobe

V

CC

Power Supply (3.3-V Typical)

V

CCQ

Power Supply for Output Drivers

(3.3-V Typical)

V

SS

Ground

V

SSQ

Ground for Output Drivers

W

Write Enable

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TMS626812B

1 048 576 BY 8-BIT BY 2-BANK

SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES

SMOS693A – OCTOBER 1997 – REVISED APRIL 1998

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the

devices, using DQM to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend the

CLK input. The device contains a mode register that must be programmed for proper operation.

Table 1, Table 2, and Table 3 show the various operations that are available on the ’626812B. These function

tables identify the command and/or operations and their respective mnemonics. Each table is followed by a

legend that explains the abbreviated symbols. An access operation refers to any read or write command in

progress at cycle n. Access operations include the cycle upon which the read or write command is entered and

all subsequent cycles through the completion of the access burst.

Table 1. Basic Command Function Table

†

COMMAND

‡

STATE OF

BANK(S)

CS RAS CAS W A11 A10 A0–A9 MNEMONIC

Mode register set

T = deac

B = deac

L L L L X X

A0–A6 = V

A7–A8 = 0

A9 = V

MRS

Bank deactivate (precharge) X L L H L BS L X DEAC

Deactivate all banks X L L H L X H X DCAB

Bank activate/row-address entry SB = deac L L H H BS V V ACTV

Column-address entry/write operation SB = actv L H L L BS L V WRT

Column-address entry/write operation

with automatic deactivate

SB = actv L H L L BS H V WRT-P

Column-address entry/read operation SB = actv L H L H BS L V READ

Column-address entry/read operation

with automatic deactivate

SB = actv L H L H BS H V READ-P

No operation X L H H H X X X NOOP

Control-input inhibit /no operation X H X X X X X X DESL

Auto-refresh

§

T = deac

B = deac

L L L H X X X REFR

†

For exception of these commands on cycle n, one of the following must be true:

– CKE(n–1) must be high.

– t

CESP

must be satisfied for power-down exit.

– t

CESP

and t

RC

must be satisfied for self-refresh exit.

– t

IS

and n

CLE

must be satisfied for clock-suspend exit.

DQM(n) is a don’t care.

‡

All other unlisted commands are considered vendor-reserved commands or illegal commands.

§

Auto-refresh or self-refresh entry requires that all banks be deactivated or be in an idle state prior to the command entry.

Legend:

n = CLK cycle number

L = Logic low

H = Logic high

X = Don’t care, either logic low or logic high

V = Valid

T = Bank T

B = Bank B

actv = Activated

deac = Deactivated

BS = Logic high to select bank T; logic low to select bank B

SB = Bank selected by A11 at cycle n

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