TI-SN54BCT8374A.pdf资源-CSDN文库

需积分: 9 166 浏览量 2022-11-28 13:02:59 上传评论 4 收藏 502KB PDF 举报

TI-SN54BCT8374A是一款由德州仪器（Texas Instruments）推出的测试集成芯片，属于SCOPE家族的一员，专门设计用于提高电路板组件的测试能力，特别是在复杂电路板组装中的边界扫描测试。这款芯片支持IEEE 1149.1-1990标准，即JTAG（Joint Test Action Group）测试访问端口和边界扫描架构。该器件集成了八位D型边沿触发触发器，正常工作模式下，它们的功能等同于传统的F374和BCT374八位D型触发器。在正常模式下，即使激活TAP（Test Access Port），也不会影响SCOPE八位触发器的正常功能。TAP是一种四线接口，用于实现对测试电路的扫描访问。在测试模式下，SCOPE八位触发器的常规操作被抑制，而测试电路被启用，允许观察并控制设备的输入/输出(I/O)边界。测试电路可以执行多种功能，包括但不限于： 1. 捕获数据快照：在特定时间点捕捉出现在设备终端上的数据状态。 2. 自我测试：对边界测试单元进行内部自我检测，检查芯片内部逻辑的正确性。 3. 并行签名分析：通过输入端进行并行签名分析，以检测电路板上多个位置的信号一致性。 4. 随机模式测试：从输出端生成伪随机测试模式，用于检测电路对外部输入的响应。 5. 样本输入/翻转输出：在控制下采样输入信号或翻转输出信号，以测试I/O路径的完整性和稳定性。 TI-SN54BCT8374A还具有一个可选的测试复位信号功能，当TMS（Test Mode Select）引脚检测到双高电平电压（10V）时，能够实施测试复位。这有助于在测试过程中进行精确的控制和初始化。封装选项包括塑料小外形(DW)封装、陶瓷芯片载体(FK)以及标准塑料(NT)和陶瓷(JT)300-mil DIP封装，满足不同应用场景的需求。 TI-SN54BCT8374A是一款专为提高电路测试效率而设计的集成电路，它结合了常规功能与测试模式，兼容IEEE 1149.1标准，提供灵活的封装选择，并具备强大的测试功能，如数据捕获、自我测试、并行签名分析和随机模式测试等，是现代电子设计中进行复杂系统级测试的重要工具。

资源推荐

资源详情

资源评论

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E − JUNE 1990 − REVISED JULY 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

D Members of the Texas Instruments

SCOPE  Family of Testability Products

D Octal Test-Integrated Circuits

D Functionally Equivalent to ’F374 and

’BCT374 in the Normal-Function Mode

D Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

D Test Operation Synchronous to Test

Access Port (TAP)

D Implement Optional Test Reset Signal by

Recognizing a Double-High-Level Voltage

(10 V) on TMS Pin

D SCOPE  Instruction Set

− IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ

− Parallel-Signature Analysis at Inputs

− Pseudo-Random Pattern Generation

From Outputs

− Sample Inputs/Toggle Outputs

D Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

description

The ’BCT8374A scan test devices with octal

edge-triggered D-type flip-flops are members of

the Texas Instruments SCOPE testability

integrated-circuit family. This family of devices

supports IEEE Standard 1149.1-1990 boundary

scan to facilitate testing of complex circuit-board

assemblies. Scan access to the test circuitry is

accomplished via the 4-wire test access port

(TAP) interface.

In the normal mode, these devices are functionally equivalent to the ’F374 and ’BCT374 octal D-type flip-flops.

The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device

terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect

the functional operation of the SCOPE octal flip-flops.

In the test mode, the normal operation of the SCOPE octal flip-flops is inhibited and the test circuitry is enabled

to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform

boundary-scan test operations as described in IEEE Standard 1149.1-1990.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

CLK

GND

TDO

TMS

TDI

TCK

SN54BCT8374A ...JT PACKAGE

SN74BCT8374A . . . DW OR NT PACKAGE

(TOP VIEW)

3212827

12 13

TDI

TCK

TMS

TDO

CLK

426

14 15 16 17

GND

SN54BCT8374A...FK PACKAGE

(TOP VIEW)

NC − No internal connection

SCOPE is a trademark of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54BCT8374A, SN74BCT8374A

SCAN TEST DEVICES

WITH OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

SCBS045E − JUNE 1990 − REVISED JULY 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Terminal Functions

TERMINAL

NAME

DESCRIPTION

CLK

Normal-function clock input. See function table for normal-mode logic. An internal pullup forces CLK to a high level if left

unconnected.

1D−8D

Normal-function data inputs. See function table for normal-mode logic. Internal pullups force these inputs to a high level if

left unconnected.

GND Ground

Normal-function output-enable input. See function table for normal-mode logic. An internal pullup forces OE to a high level

if left unconnected.

1Q−8Q Normal-function data outputs. See function table for normal-mode logic.

TCK

Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to

TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. An internal pullup forces

TCK to a high level if left unconnected.

TDI

Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through

the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.

TDO

Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data

through the instruction register or selected data register. An internal pullup forces TDO to a high level when it is not active

and is not driven from an external source.

TMS

Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP

controller states. An internal pullup forces TMS to a high level if left unconnected. TMS also provides the optional test reset

signal of IEEE Standard 1149.1-1990. This is implemented by recognizing a third logic level, double high (V

IHH

), at TMS.

Supply voltage

剩余25页未读，继续阅读

评论收藏

内容反馈

不觉明了

粉丝: 7270
资源: 5764

TI-SN54BCT8374A.pdf

TI-SN74BCT8244A.pdf

TI-SN74BCT8240A.pdf

TI-SN74BCT8373A.pdf

xm.bct.txt

tegra k1 开发板的bct文件xm.bct

RV2C014BCT2CL.pdf

TI公司_逻辑器件选型手册.pdf

BW310-BW310.pdf

BCT644 (1).pdf

BCT3288A手册

FANUC数控系统31i-B参数说明书（非常详细）.pdf

BCT_复杂网络matlab_BCT_BCT工具_

BCT_v2015.rar_BCT_FJ9_图论参数计算

论文研究-MSN网络的优化问题研究.pdf

bct4480-i2c.c

matlab如何敲代码-A-SIMPLE-TUTORIAL-TO-START-WITH-FUNCTIONAL-NETWORKS.:我们到了！主

泰山版初一信息python练习题-(1)(1).doc

论文研究-Metaphor Applied to the Study of Lexical Semantic Structure.pdf

A-SIMPLE-TUTORIAL-TO-START-WITH-FUNCTIONAL-NETWORKS.:我们到了！ 主要思想是我们如何从 EEG 记录数据库建立一个功能性大脑网络，然后可视化一些网络-matlab开发

相关实用应用程序（Windows可用）

李飞飞自传 我看见的世界 The World I see

ChatGPT使用总结：150个ChatGPT提示词模板（完整版）

全国计算机二级WPSoffice精选350道选择题题库（含答案）.pdf

Visio2013 安装包及破解方法

DBeaver 序列码， DBeaver Ultimate 24.3.0 可用

哈尔滨工业大学-ChatGPT调研报告-2023.3.6-94页.pdf

eetop.cn-07-1射频电路设计理论与应用-王子宇 -课后答案1-10章

学术海报模板+论文科研+研究生

4个亲测好用的ChatGPT4渠道

最新资源

A-SIMPLE-TUTORIAL-TO-START-WITH-FUNCTIONAL-NETWORKS.:我们到了！主要思想是我们如何从 EEG 记录数据库建立一个功能性大脑网络，然后可视化一些网络-matlab开发

李飞飞自传我看见的世界 The World I see