/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V1.4.0
* @date 04-August-2014
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F4xx devices.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F40xxx/41xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 168000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Main regulator output voltage | Scale1 mode
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Disabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
*=============================================================================
* Supported STM32F42xxx/43xxx devices
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 180000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 360
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 7
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------
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STM32+超声波模块+RGB
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基于STM32为基础,通过超声波模块测量距离大小,从而控制RGB的颜色。
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STM32+超声波模块+RGB (103个子文件)
HZJ.uvguix.23206 183KB
HZJ.axf 360KB
HZJ_sct.Bak 494B
system_stm32f4xx.c 47KB
pwm.c 7KB
capture.c 5KB
led.c 5KB
usart1.c 5KB
usart2.c 4KB
exti.c 3KB
delay.c 2KB
key.c 2KB
tim7.c 1KB
systick.c 1KB
main.c 1KB
beep.c 705B
ir.c 520B
pwm.crf 270KB
capture.crf 269KB
led.crf 268KB
usart1.crf 268KB
delay.crf 267KB
usart2.crf 267KB
key.crf 267KB
exti.crf 266KB
tim7.crf 266KB
systick.crf 266KB
beep.crf 266KB
ir.crf 266KB
main.crf 266KB
system_stm32f4xx.crf 258KB
capture.d 1KB
systick.d 1KB
usart2.d 1KB
usart1.d 1KB
delay.d 1KB
exti.d 1KB
tim7.d 1KB
beep.d 1KB
main.d 1KB
led.d 1KB
key.d 1KB
pwm.d 1KB
ir.d 1KB
system_stm32f4xx.d 494B
startup_stm32f40_41xxx.d 71B
Target_1_STM32F407VETx.dbgconf 2KB
Project_ByHZJ_STM32F407VETx.dbgconf 2KB
HZJ_Project_ByHZJ.dep 20KB
stm32f4xx.h 688KB
arm_math.h 237KB
core_cm4.h 107KB
core_cm3.h 97KB
core_sc300.h 96KB
core_sc000.h 41KB
core_cm0plus.h 39KB
core_cm0.h 32KB
core_cm4_simd.h 22KB
core_cmInstr.h 20KB
core_cmFunc.h 17KB
arm_common_tables.h 5KB
arm_const_structs.h 4KB
system_stm32f4xx.h 2KB
led.h 821B
usart1.h 481B
usart2.h 459B
includes.h 355B
key.h 351B
systick.h 307B
pwm.h 285B
exti.h 267B
capture.h 242B
beep.h 182B
main.h 159B
ir.h 151B
delay.h 129B
tim7.h 121B
HZJ.htm 54KB
HZJ.build_log.htm 2KB
HZJ.uvguix.Kevin_Best 87KB
HZJ.lnp 598B
startup_stm32f40_41xxx.lst 75KB
HZJ.map 80KB
usart1.o 301KB
capture.o 300KB
pwm.o 299KB
usart2.o 298KB
exti.o 297KB
led.o 294KB
tim7.o 292KB
systick.o 291KB
delay.o 290KB
main.o 290KB
key.o 290KB
beep.o 289KB
ir.o 289KB
system_stm32f4xx.o 276KB
startup_stm32f40_41xxx.o 8KB
startup_stm32f40_41xxx.s 29KB
HZJ.sct 479B
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