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High Bandwidth NAND
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High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology
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High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN)
with the Bumpless TSV Technology
Koji Sakui
1),2)
1)
Tokyo Institute of Technology, IIR, WOW Alliance
Yokohama, Japan sakui.k.aa@m.titech.ac.jp
2)
Honda Research Institute Japan Co., Ltd.
Wako-shi, Japan koji.sakui@jp.honda-ri.com
Takayuki Ohba
1)
1)
Tokyo Institute of Technology, IIR, WOW Alliance
Yokohama, Japan
ohba.t.ac@m.titech.ac.jp
Abstract— This paper proposes a fundamental architecture for
the High Bandwidth Memory (HBM) with the bumpless TSV for
the Wafer-on-Wafer (WOW) technology. The bumpless
interconnects technology can increase the number of TSVs per
chip with fine pitch of TSVs, and reduce the impedance of the TSV
interconnects with no bumps. Therefore, a further higher speed
and higher density HBM can be realized. Also, the High
Bandwidth NAND (HBN), which can read and program by plane
instead of by line by using the bumpless TSV, has been proposed.
Keywords—wafer-on-wafer; bumpless; thinning; TSV; high
density integration; HBM; HBN
I. INTRODUCTION
TSVs with micro-bumps are conventionally used for the
High Bandwidth Memory (HBM) [1-4]. However, there are
several issues using the micro-bumps. One major problem is that
it should be difficult for even the HBM to catch up with the
speed of the GPU or CPU. For example, the Pascal of NVIDIA
is 1TB/s, so that four sets of the HBM with 256GB/s are forced
to use for the operation of the Pascal. The GPU/CPU venders are
challenging their products speed up much more, like 2TB/s and
4TB/s, for emphasizing the AI system, such as an advanced
automated driving. However, the HBM speed should be getting
almost saturated to 341GB/s [4].
On the other hand, the 3D stacking, in combination with the
conventional 2D integration, has been studied extensively [5-8],
because it is well understandable that the conventional two-
dimensional (2D) scaling should be forced to face with a severe
economic crisis due to the expensive lithography process and
facilities required. However, reducing the TSV pitch and
impedance has not been focused on in details. This paper is
devoted to increasing the number of TSVs per chip with fine
pitch of TSVs, and reducing the impedance of the TSV
interconnects with no bumps [9-14]. As a result, a further higher
speed and higher density HBM, and the High Bandwidth NAND
(HBN) by using the bumpless TSV, can been proposed [15-16].
II. B
ENEFITS OF 3D STACKED MEMORIES WITH BUMPLESS TSV
1. Shorten Physical Wiring Length
Fig. 1 illustrates the wiring length comparison between the
2D and 3D. In the 3D layout, the block-to-block length is 10 ~
100 μm, while that of the 2D layout is 1 mm ~ 1 cm.
Fig. 1 Wiring length comparison between the 2D and 3D.
2. Thin Die Thickness
Fig. 2 shows the die thickness comparison between the 2D
and 3D. Because the bump is very large, the die thickness of at
least 30 μm is needed for the robust stiffness. As a result, the
stacked chip pitch is something like 100 μm. If 16 chips are
stacked, the total height should be 1600 μm. On the contrary,
thanks to the bumpless technology, the chip pitch becomes one
tenths. Therefore, the total height of the 16 chip stacked case
would be only 160 μm.
Fig. 2 Die thickness comparison between the 2D and 3D.
978-1-7281-4870-0/19/$31.00@2019IEEE
3DIC2019.4005
2019International3DSystemsIntegrationConference(3DIC)
Authorized licensed use limited to: Fondren Library Rice University. Downloaded on May 17,2020 at 03:57:53 UTC from IEEE Xplore. Restrictions apply.
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