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SY5605规格书,希望对大家有帮助
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SY5605规格书,希望对大家有帮助
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Application Note: SY5605
PoE PD Interface and DC-DC Flyback Controller
Preliminary Specification
AN_SY5605 Rev.0.1 Silergy Corp. Confidential- Prepared for Customer Use Only 1
© 2019 Silergy Corp. All Rights Reserved.
General Description
The SY5605 is a combined Power over Ethernet (PoE)
powered device (PD) interface and primary side
controller optimized specifically for isolated converter
designs. The SY5605 supports the IEEE 802.3 at
standard, 25W powered device. Suitable external
resistors connected to the SY5605 provide the proper
IEEE 802.3 signatures for the detection function and
programming of the classification mode.
To achieve higher efficiency and better EMI
performance, SY5605 drives Flyback converters in the
Quasi-Resonant mode and adaptive PWM/PFM control.
Ordering Information
Package Code
Temperature Code
Optional Spec Code
□
(
□□
)
□
SY5605
Features
Power up to 25W
Supports the IEEE 802.3at and 802.3af Standard
Primary Side Control for DC/DC Controller
QR-mode Operation for High Efficiency
PWM/PFM Control for Higher Average Efficiency
Adapter ORing Support
95V, 0.4Ω Hotswap MOSFET
RoHS Compliant and Halogen Free
Compact Package: QFN4*4-20
Applications
IEEE 802.3at and 802.3af Compliant Devices
Video and VoIP Telephones
RFID Readers
Multiband Access Points
Security Cameras
Typical Applications
Adapter
From Ethernet
1-2,3-6
From Ethernet
4-5,7-8
Z1
R
DEN
R
APD2
R
APD1
D
A
C
1
C
VCC
R
SENS
C
OUT
V
OUT
C
IN
D
VC1
T
1
M
1
RTN
CS
GATE
VCC
DEN
CLS
VSS
APD
ZCS
R
VC1
R
ZCS1
R
ZCS2
VDD T2P
R
T2P
R
CLS
R
CS
D
1
LED
1
D
2
C
2
Ordering Number
Package type
Note
SY5605QYC
QFN4*4-20
----
![](https://csdnimg.cn/release/download_crawler_static/89051229/bg2.jpg)
AN_SY5605
AN_SY5605 Rev.0.1 Silergy Corp. Confidential- Prepared for Customer Use Only 2
© 2019 Silergy Corp. All Rights Reserved.
Pinout (top view)
NC
6
7
8
9
VDD
APD
ZCS
NC
VSS
NC
Exposed
Pad
DEN
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
NC
NC
CS
CLS
GATE
NC
NC
RTN
VCC
T2P
NC
NC
(QFN4*4-20)
Top Mark: CKZxyz (device code: CKZ, x=year code, y=week code, z= lot number code)
Name
Pin
Description
VDD
1
Connect to the positive PoE input power rail. VDD powers the PoE interface circuits. Bypass with
a 0.1 μF capacitor and protect with a TVS.
DEN
3
Connect a 24.9 kΩ resistor from DEN to VDD to provide the PoE detection signature. Pulling this
pin to VSS during powered operation causes the internal hotswap MOSFET to turn off.
CLS
4
Connect a resistor from CLS to VSS to program classification current. 2.5 V is applied to the
program resistor during classification to set class current.
APD
5
Pull APD above 1.5 V disables the internal hotswap switch. Forcing power to come from an
external adapter. Connect APD to RTN when not used.
GATE
6
Gate drive pin.
CS
9
Current sense pin.
ZCS
11
Inductor current zero-crossing detection pin. This pin receives the auxiliary winding voltage by a
resistor divider and detects the inductor current zero crossing point.
VCC
12
DC/DC converter bias voltage.
T2P
13
Active low output that indicates a PSE has performed the IEEE 802.3at type 2 hardware
classification, or APD is active
RTN
15
RTN is the negative rail input to the dc/dc converter, and output of the PoE hotswap MOSFET.
VSS
17
Connect to the negative power rail derived from the PoE source.
Exposed Pad
This is the thermal flag for the IC and should be soldered to the plane which is connected to VSS.
NC
others
Not connect.
![](https://csdnimg.cn/release/download_crawler_static/89051229/bg3.jpg)
AN_SY5605
AN_SY5605 Rev.0.1 Silergy Corp. Confidential- Prepared for Customer Use Only 3
© 2019 Silergy Corp. All Rights Reserved.
Absolute Maximum Ratings
(1)
Input voltage range [DEN, VDD, RTN
(2)
] to VSS ------------------------------------------------------------------------ -0.3-95V
Input voltage range [VDD, T2P] to RTN ----------------------------------------------------------------------------------- -0.3-95V
Input voltage range VCC to RTN -------------------------------------------------------------------------------------------- -0.3-25V
Input voltage range CLS
(3)
to VSS----------------------------------------------------------------------------------------- -0.3- 5.5V
Input voltage range [ZCS, CS, APD] to RTN ---------------------------------------------------------------------------- -0.3- 5.5V
Input voltage range GATE to RTN ----------------------------------------------------------------------------------------- -0.3- 15V
Package Thermal Resistance
(4)
QFN4*4-20, θ
JA
----------------------------------------------------------------------------------------------------- 45°C/W
QFN4*4-20, θ
JC
--------------------------------------------------------------------------------------------------- 22.5°C/W
Junction Temperature Range ---------------------------------------------------------------------------------------- -45°C to 150°C
Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------------------------- 260°C
Storage Temperature Range ------------------------------------------------------------------------------------------ -65°C to 150°C
Recommended Operating Conditions
Input voltage range [RTN, VDD] to VSS-------------------------------------------------------------------------------------- 0- 72V
Input voltage range VDD to RTN ---------------------------------------------------------------------------------------------- 0- 72V
Input voltage range VCC to RTN ---------------------------------------------------------------------------------------------- 0- 18V
Junction Temperature Range ------------------------------------------------------------------------------------------ -40°C to 125°C
Notes:
(1): Stresses beyond the “Absolute Maximum Ratings” may cause perm anent damage to the device. These
are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2): I
RTN
=0 for V
RTN
>80V.
(3): Do not apply voltage to this pin.
(4): JESD 51-2,-5,-7,-8,-14 standard.
![](https://csdnimg.cn/release/download_crawler_static/89051229/bg4.jpg)
AN_SY5605
AN_SY5605 Rev.0.1 Silergy Corp. Confidential- Prepared for Customer Use Only 4
© 2019 Silergy Corp. All Rights Reserved.
Block Diagram
Softstart
enb
PWM
generator
GATE
VDD
Classification
Logic&
Regulator
CLS
DEN
VSS
Control
VSS
RTN
APD
VCC
CS
V
O
Estimator
Valley
Detect
gm
ZCS
VDD
COMP
RTN
IPK_Sense
ZCS_FB
Valley_DET
PWM
COMP Behavior
(Frequency_ set、
Ipk_set)
Flimit_SET
IPK_SET
Valley_DET
IPK_Sense
enb
SS
Protection
VCC_OVP
ZCS_OVP
IPK_SEN
Latchoff
Hiccup
Detection
Control logic
& Inrush and
current limit
Current
sense
Type2
States
T2P
RTN
T2P
Logic
Mark Event
ZCS_OVP
ZCS_REF
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