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4th-gen-epyc-processor-architecture-white-paper
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4th-gen-epyc-processor-architecture-white-paper
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2READY TO CONNECT? Visit explore.amd.com/server-newsletter/sign-up
4TH GEN AMD EPYC PROCESSOR
ARCHITECTURE
CONTENTS
INTRODUCTION �������������������������������������������������������������������������������������������������������������� � 3
HYBRID MULTI-DIE ARCHITECTURE ��������������������������������������������������������������������������� � 4
Decoupled Innovation Paths � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 4
‘Zen 4’ Core � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 5
‘Zen 4c’ Core � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 5
Modularity Enables Innovation � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 5
Simplified Production � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 7
I/O Die Innovation � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 7
AMD Infinity Architecture � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 7
4TH GEN EPYC PROCESSOR CORES ����������������������������������������������������������������������������� 8
‘Zen 4’ CPU Die � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 8
‘Zen 4c’ CPU Die � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 8
Double-Digit IPC Improvements � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 8
AVX-512 Instructions � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 8
Larger Addressable Memory � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 9
Security Enhancements � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 9
SYSTEM-ON-CHIP DESIGN ������������������������������������������������������������������������������������������ � 10
AMD Infinity Fabric™ Technology and the I/O Die SERDES � � � � � � � � � � � � � � � � � � � � � 11
NUMA Considerations � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 12
MULTIPROCESSOR SERVER DESIGNS ������������������������������������������������������������������������ 13
Single-Socket Server Configurations � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 13
2-Socket Server Configurations � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 13
AMD INFINITY GUARD FEATURES ���������������������������������������������������������������������������� � 14
Cutting-Edge Security Features � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 14
AMD Secure Processor � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � 14
CONCLUSION ������������������������������������������������������������������������������������������������������������������� 16
3READY TO CONNECT? Visit explore.amd.com/server-newsletter/sign-up
The information technology industry is changing rapidly, with
many dierent workload facets demanding innovation that can
satisfy their specific needs� High-performance computing and cloud
applications need high-density CPUs with high core counts for
highly parallelized workloads� Enterprise applications need a balance
between CPU and I/O capability� Artificial intelligence, data analytics,
high-performance computing, as well as structured and unstructured
data applications are driven by the strength and speed of individual
cores and accelerated mathematical functions� Certain cloud,
manufacturing, healthcare, retail, telco, and other edge applications
need highly ecient computing that can operate in challenging
environments, from closets in retail stores to telephone switching
and cellular transmission locations� And network infrastructure,
security, and edge applications need cost-and power-optimized
systems that can be deployed confidently in locations around the
globe�
The design decisions we have made in the 4th generation of AMD
EPYC™ processors have evolved a platform that can support all of
these needs� The following goals have driven the design of the AMD
EPYC 8004 and 9004 Series processors:
• INSTRUCTIONS-PER-CLOCK (IPC) improvements, ranging in double-
digit increases across generations
• EXCELLENT EFFICIENCY, with leadership performance per watt
• BALANCED ARCHITECTURE, with high memory bandwidth and I/O
capacity to match the CPU’s voracious appetite for data
• LOW LATENCY, with a goal of reducing average latency with higher
cache sizes and eectiveness
• HIGH THROUGHPUT, with a goal of reducing dynamic power to
enable significantly higher core counts
This white paper describes the processor architecture that supports
4th Gen AMD EPYC processors and future enhancements that enable
you to branch out and address a continuously widening universe of
workload demands� Our hybrid, multi-chip architecture enables us to
decouple innovation paths and deliver consistently innovative, high-
performance products� The ‘Zen 4’ and ‘Zen 4c’ cores represent a
significant advancement from the last generation, with new support
for highly complex machine learning and inferencing applications�
Our system-on-chip approach helps server vendors to accelerate
their designs and get innovative products into customers’ hands
quickly� AMD EPYC processors are the only x86 server CPUs with
an integrated, embedded security processor that is “hardened at
the core” to help secure customer data whether in a central data
center or distributed across locations at the network edge� Finally,
this paper will review some of the design choices that enable
no-compromise single-socket servers as well as some of the most
powerful two-socket servers on the planet�
INTRODUCTION
4READY TO CONNECT? Visit explore.amd.com/server-newsletter/sign-up
HYBRID MULTI-DIE ARCHITECTURE
The most important innovation in AMD EPYC processors is the hybrid
multi-die architecture first introduced in 2nd Gen EPYC processors�
We anticipated the fact that increasing core density in monolithic
processor designs would become more dicult over time� One of
the primary issues is the fact that the process technology that
can create a CPU core is on a dierent innovation path than the
technology that lays down the analog circuitry to drive external
pathways to memory, I/O devices, and an optional second processor�
These two technologies are linked together when creating monolithic
processors and can impede the swift delivery of products to market�
DECOUPLED INNOVATION PATHS
Second, third, and fourth-Gen AMD EPYC processors have
decoupled the innovation paths for CPU cores and I/O functions
into two dierent types of dies that can be developed on timelines
appropriate for what they need to do� For example, the ‘Zen 4’ cores
are produced with 5nm technology and the I/O die is created with
6nm processes� This decoupling has enabled higher core densities
within the same thermal envelope� Continuous improvement in
instructions per cycle has yielded double-digit performance gains
with every new generation (Table1)� The approach we have taken
is more flexible and dynamic than trying to force all aspects of a
processor into one fabrication technology� We believe that it is
faster to deliver high-performance products and specialized CPUs to
market by assembling modules into a processor than to create large,
monolithic CPUs�
In today’s 4th Gen AMD EPYC processors we use two dierent
cores to address a range of workload needs by varying the type
and number of cores and how we package them� The EPYC 9004
Series uses an SP5 form factor and processors within this series use
either the ‘Zen 4’ or ‘Zen 4c’ core designs� The EPYC 8004 Series
Table 1: The multi-die architecture has enabled significant improvements for each processor generation since the beginning
AMD EPYC 7001
‘NAPLES’
AMD EPYC 7002
‘ROME’
AMD EPYC 7003
‘MILAN’
AMD EPYC 9004, 8004
‘GENOA’, ‘SIENA’
Core Architecture ‘Zen’ ‘Zen 2’ ‘Zen 3’ ‘Zen 4’ and ‘Zen 4c’
Cores 8 to 32 8 to 64 8 to 64 8 to 128
IPC Improvement Over
Prior Generation
N/A ~24%
ROM-236
~19%
MLN-003
~14%
EPYC-038
Max L3 Cache Up to 64 MB Up to 256 MB Up to 256 MB
Up to 384 MB (EPYC 9004)
Up to 128 MB (EPYC 8004)
Max L3 Cache with 3D V-Cache™ technology 768 MB Up to 1152 MB
PCIe® Lanes Up to 128 Gen 3 Up to 128 Gen 3 Up to 128 Gen 4
Up to 128 Gen 5
8 bonus lanes Gen 3
CPU Process Technology 14nm 7nm 7nm 5nm
I/O Die Process Technology N/A 14nm 14nm 6nm
Power (Configurable TDP [cTDP]) 120-200W 120-280W 155-280W 70-400W
Max Memory Capacity 2 TB DDR3-2400/2666 4 TB DDR4-3200 4 TB DDR4-3200 6 TB DDR5-4800
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