Xuantie IOMMU Specification Version 1.0 (Draft)
Siqi Zhao
February 28, 2022
This document describes an IOMMU design specification for the Xuantie platform, which is
based on harts of the RISC-V architecture.
An IOMMU is used to translate virtual addresses in DMA requests from external devices
connected on certain peripheral bus to physical addresses. Abstractly, for all addresses that
can be accessed by an entity identified by a source ID, the IOMMU maintains a relation
from the tuple (source ID, virtual address) to a physical address.
The source ID identifies the entity that initiates DMA operations. The exact meaning of the
entity is dependent on the peripheral bus that the IOMMU is interfaced with. For example,
when the IOMMU is used to translate virtual addresses from a PCI-Express device, the
entity may refers to the device functions in the PCI-Express device. For simplicity, the rest
of this document refers to such an entity as a device. It is also assumed that one device is
only capable of generating DMA operations tagged with one unique identifier.
NOTE: It is up to the implementation to define the exact entity that the term ’device’
refers to.
The IOMMU utilizes a table structure to maintain the aforementioned mapping relation.
The table structure could be implemented as register arrays or as memory resident data
structure. The table structure consists of multiple levels of tables. There are two types of
tables, the upper levels are IOMMU-specific look-up tables indexed by the source IDs. The
lower level tables contain entries that are the same as the page table entries as defined in
the RISC-V privileged architecture.
NOTE: Typically, peripheral devices assigned to a virtual machine can also send interrupts
that target the harts of that virtual machine, and these interrupts need to be routed as
well, however, this design only specifies the DMA address translations. For interrupts, the
Advanced Interrupt Architecture (AIA) already includes the capability to redirect interrupts
from the devices to specific harts.
The address translation can be performed with either one stage or two stages. An operating
system kernel may utilize one-stage translation to directly assigned a device to a process.
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