MISC Architecture Specification v1.0
Sanechips Confidential 2023/06/29 2
Revision History:
目录
1Overview ............................................................................................................................................................4
1.1 block diagram: .................................................................................................................................................4
1.2 Acronyms .........................................................................................................................................................5
1.3 AIA 功能说明...................................................................................................................................................5
2 AIA Top Architecture..........................................................................................................................................5
2.1 AIA Top Interfaces ...........................................................................................................................................6
2.1.1 APLIC 接口.......................................................................................................................................6
2.1.2 APLIC 接口时序图...........................................................................................................................9
2.1.3 IMSIC 接口.....................................................................................................................................10
2.1.4 IMSIC 接口时序图.........................................................................................................................13
2.2 AIA main flow.................................................................................................................................................14
2.2.1 APLIC IDC flow ...............................................................................................................................14
2.2.2 APLIC IDC （legacy）flow .............................................................................................................16
2.2.3 APLIC IMSIC flow............................................................................................................................17
3 子模块设计 .....................................................................................................................................................18
3.1 APLIC 子模块设计 .........................................................................................................................................18
3.1.1 APLIC 模块划分.............................................................................................................................18
3.1.2 aplic_gateway 逻辑设计...............................................................................................................19
3.1.3 aplic_intr_route 逻辑设计 ............................................................................................................20
3.1.4 aplic_regfile 逻辑设计 ..................................................................................................................22
3.2 IMSIC 子模块设计.........................................................................................................................................24
3.2.1 IMSIC 模块划分.............................................................................................................................24
3.3 BUS 子模块设计............................................................................................................................................39
3.3.1 MSI 中断在 CMN 中传输过程......................................................................................................39
3.3.2 AXI4_Stream 与 pub 数据转换.....................................................................................................40
3.4 CLINT timer 模块设计 ...................................................................................................................................42
3.4.1 timer 模块功能 .............................................................................................................................42
3.4.2 timer 模块接口信号 .....................................................................................................................43
3.4.3 timer 模块数据流 .........................................................................................................................44
3.4.4 timer 模块寄存器 .........................................................................................................................45
3.5 模块寄存器说明 ...........................................................................................................................................45
3.5.1 AIA 架构下新增的 CSR..................................................................................................................45
3.5.2 CSRs for external interrupts via an IMSIC ......................................................................................46
3.5.3 Indirectly accessed interrupt-file registers ....................................................................................48
