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DataSheet 部分模拟接口扩展功能
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SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
Very Low Noise, 24-Bit
Analog-to-Digital Converter
ADS1255
ADS1256
FEATURES
D 24 Bits, No Missing Codes
− All Data Rates and PGA Settings
D Up to 23 Bits Noise-Free Resolution
D ±0.0010% Nonlinearity (max)
D Data Output Rates to 30kSPS
D Fast Channel Cycling
− 18.6 Bits Noise-Free (21.3 Effective Bits)
at 1.45kHz
D One-Shot Conversions with Single-Cycle
Settling
D Flexible Input Multiplexer with Sensor Detect
− Four Differential Inputs (ADS1256 only)
− Eight Single-Ended Inputs (ADS1256 only)
D Chopper-Stabilized Input Buffer
D Low-Noise PGA: 27nV Input-Referred Noise
D Self and System Calibration for All PGA
Settings
D 5V Tolerant SPI™-Compatible Serial Interface
D Analog Supply: 5V
D Digital Supply: 1.8V to 3.6V
D Power Dissipation
− As Low as 38mW in Normal Mode
− 0.4mW in Standby Mode
APPLICATIONS
D Scientific Instrumentation
D Industrial Process Control
D Medical Equipment
D Test and Measurement
D Weigh Scales
DESCRIPTION
The ADS1255 and ADS1256 are extremely low-noise,
24-bit analog-to-digital (A/D) converters. They provide
complete high-resolution measurement solutions for the
most demanding applications.
The converter is comprised of a 4th-order, delta-sigma
(ΔΣ) modulator followed by a programmable digital filter. A
flexible input multiplexer handles differential or
single-ended signals and includes circuitry to verify the
integrity of the external sensor connected to the inputs.
The selectable input buffer greatly increases the input
impedance and the low-noise programmable gain
amplifier (PGA) provides gains from 1 to 64 in binary steps.
The programmable filter allows the user to optimize
between a resolution of up to 23 bits noise-free and a data
rate of up to 30k samples per second (SPS). The
converters offer fast channel cycling for measuring
multiplexed inputs and can also perform one-shot
conversions that settle in just a single cycle.
Communication is handled over an SPI-compatible serial
interface that can operate with a 2-wire connection.
Onboard calibration supports both self and system
correction of offset and gain errors for all the PGA settings.
Bidirectional digital I/Os and a programmable clock output
driver are provided for general use. The ADS1255 is
packaged in an SSOP-20, and the ADS1256 in an
SSOP-28.
SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
www.ti.com
Copyright © 2003−2013, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
XTAL2
Serial
Interface
Mux
and
Sensor
Detect
Programmable
Digital Filter
4th−Order
Modulator
VREFP VREFN
ADS1256 Only
ADS1256
Only
Buffer
AVDD DVDD
1:64
DGND
D3 D2 D1 D0/CLKOUTAGND
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
XTAL1/CLKIN
RESET
DRDY
SCLK
DIN
SYNC/PDWN
CS
DOUT
Control
General
Purpose
Digital I/O
Clock
Generator
PGA
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
2
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
ADS1255, ADS1256 UNIT
AVDD to AGND −0.3 to +6 V
DVDD to DGND −0.3 to +3.6 V
AGND to DGND −0.3 to +0.3 V
Input Current
100, Momentary mA
Input Current
10, Continuous mA
Analog inputs to AGND −0.3 to AVDD + 0.3 V
Digital
inputs
DIN, SCLK, CS, RESET,
SYNC/PDWN,
XTAL1/CLKIN to DGND
−0.3 to +6 V
inputs
D0/CLKOUT, D1, D2, D3
to DGND
−0.3 to DVDD + 0.3 V
Maximum Junction Temperature +150 °C
Operating Temperature Range −40 to +105 °C
Storage Temperature Range −60 to +150 °C
Lead Temperature (soldering, 10s) +300 °C
(1)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond
those specified is not implied.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
3
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V
REF
= +2.5V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Inputs
Full-scale input voltage (AIN
P
− AIN
N
) ±2V
REF
/PGA V
Absolute input voltage
Buffer off AGND − 0.1 AVDD + 0.1 V
Absolute input voltage
(AIN0-7, AINCOM to AGND)
Buffer on AGND AVDD − 2.0 V
Programmable gain amplifier 1 64
Buffer off, PGA = 1, 2, 4, 8, 16 150/PGA kΩ
Differential input impedance
Buffer off, PGA = 32, 64 4.7 kΩ
pp
Buffer on, f
DATA
≤ 50Hz
(1)
80 MΩ
SDCS[1:0] = 01 0.5 μA
Sensor detect current sources
SDCS[1:0] = 10 2 μA
SDCS[1:0] = 11 10 μA
System Performance
Resolution 24 Bit
No missing codes All data rates and PGA settings 24 Bit
Data rate (f
DATA
) f
CLKIN
= 7.68MHz 2.5 30,000 SPS
(2)
Integral nonlinearity
Differential input, PGA = 1 ±0.0003 ±0.0010 %FSR
(3)
I
ntegra
l
non
li
near
i
ty
Differential input, PGA = 64 ±0.0007 %FSR
Offset error After calibration On the level of the noise
Offset drift
PGA = 1 ±100 nV/°C
Off
set
d
r
if
t
PGA = 64 ±4 nV/°C
Gain error
After calibration, PGA = 1, Buffer on ±0.005 %
G
a
i
n
error
After calibration, PGA = 64, Buffer on ±0.03 %
Gain drift
PGA = 1 ±0.8 ppm/°C
G
a
i
n
d
r
if
t
PGA = 64 ±0.8 ppm/°C
Common-mode rejection f
CM
(4)
= 60Hz, f
DATA
= 30kSPS
(5)
95 110 dB
Noise See Noise Performance Tables
AVDD power-supply rejection ±5% Δ in AVDD 60 70 dB
DVDD power-supply rejection ±10% Δ in DVDD 100 dB
Voltage Reference Inputs
Reference input voltage (V
REF
) V
REF
≡ VREFP − VREFN 0.5 2.5 2.6 V
Negative reference input (VREFN)
Buffer off AGND − 0.1 VREFP − 0.5 V
N
egat
i
ve
re
f
erence
i
nput
(VREFN)
Buffer on
(6)
AGND VREFP − 0.5 V
Positive reference input (VREFP)
Buffer off VREFN + 0.5 AVDD + 0.1 V
P
os
i
t
i
ve
re
f
erence
i
nput
(VREFP)
Buffer on
(6)
VREFN + 0.5 AVDD − 2.0 V
Voltage reference impedance f
CLKIN
= 7.68MHz 18.5 kΩ
Digital Input/Output
V
IH
DIN, SCLK, XTAL1/CLKIN,
SYNC/PDWN, CS, RESET
0.8 DVDD 5.25 V
V
IH
D0/CLKOUT, D1, D2, D3 0.8 DVDD DVDD V
V
IL
DGND 0.2 DVDD V
V
OH
I
OH
= 5mA 0.8 DVDD V
V
OL
I
OL
= 5mA 0.2 DVDD V
Input hysteresis 0.5 V
Input leakage 0 < V
DIGITAL
INPUT
< DVDD ±10 μA
Master clock rate
External crystal between XTAL1 and
XTAL2
2 7.68 10 MHz
Master clock rate
External oscillator driving CLKIN 0.1 7.68 10 MHz
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
4
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V
REF
= +2.5V, unless otherwise noted.
PARAMETER UNITMAXTYPMINTEST CONDITIONS
Power-Supply
AVDD 4.75 5.25 V
DVDD 1.8 3.6 V
Power-down mode 2 μA
Standby mode 20 μA
AVDD current
Normal mode, PGA = 1, Buffer off 7 10 mA
AVDD current
Normal mode, PGA = 64, Buffer off 16 22 mA
Normal mode, PGA = 1, Buffer on 13 19 mA
Normal mode, PGA = 64, Buffer on 36 50 mA
Power-down mode 2 μA
DVDD current
Standby mode, CLKOUT off,
DVDD = 3.3V
95 μA
Normal mode, CLKOUT off,
DVDD = 3.3V
0.9 2 mA
Power dissipation
Normal mode, PGA = 1, Buffer off,
DVDD = 3.3V
38 57 mW
Power dissipation
Standby mode, DVDD = 3.3V 0.4 mW
Temperature Range
Specified −40 +85 °C
Operating −40 +105 °C
Storage −60 +150 °C
(1)
See text for more information on input impedance.
(2)
SPS = samples per second.
(3)
FSR = full-scale range = 4V
REF
/PGA.
(4)
f
CM
is the frequency of the common-mode input signal.
(5)
Placing a notch of the digital filter at 60Hz (setting f
DATA
= 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve the
common-mode rejection of this frequency.
(6)
The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration or
writing calibration values directly to the registers, the entire Buffer off range can be used.
ADS1255
ADS1256
SBAS288K − JUNE 2003 − REVISED SEPTEMBER 2013
www.ti.com
5
PIN ASSIGNMENTS
SSOP PACKAGE
(TOP VIEW)
ADS1255 ADS1256
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
AIN1
SYNC, PDWN
RESET
DVDD
D1
D0/CLKOUT
SCLK
DIN
DOUT
DRDY
CS
XTAL1/CLKIN
XTAL2
DGND
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
AIN1
SYNC, PDWN
RESET
DVDD
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
D3
D1
D2
D0/CLKOUT
DIN
SCLK
DOUT
CS
DRDY
XTAL1/CLKIN
DGND
XTAL2
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
9
8
7
6
5
4
3
2
1
10
13
12
11
14
20
21
22
23
24
25
26
27
28
19
16
17
18
15
Terminal Functions
TERMINAL NO.
ANALOG/DIGITAL
NAME ADS1255 ADS1256
ANALOG/DIGITAL
INPUT/OUTPUT
DESCRIPTION
AVDD 1 1 Analog Analog power supply
AGND 2 2 Analog Analog ground
VREFN 3 3 Analog input Negative reference input
VREFP 4 4 Analog input Positive reference input
AINCOM 5 5 Analog input Analog input common
AIN0 6 6 Analog input Analog input 0
AIN1 7 7 Analog input Analog input 1
AIN2 — 8 Analog input Analog input 2
AIN3 — 9 Analog input Analog input 3
AIN4 — 10 Analog input Analog input 4
AIN5 — 11 Analog input Analog input 5
AIN6 — 12 Analog input Analog input 6
AIN7 — 13 Analog input Analog input 7
SYNC/PDWN 8 14 Digital input
(1)(2)
: active low Synchronization / power down input
RESET 9 15 Digital input
(1)(2)
: active low Reset input
DVDD 10 16 Digital Digital power supply
DGND 11 17 Digital Digital ground
XTAL2 12 18 Digital
(3)
Crystal oscillator connection
XTAL1/CLKIN 13 19 Digital/Digital input
(2)
Crystal oscillator connection / external clock input
CS 14 20 Digital input
(1)(2)
: active low Chip select
DRDY 15 21 Digital output: active low Data ready output
DOUT 16 22 Digital output Serial data output
DIN 17 23 Digital input
(1)(2)
Serial data input
SCLK 18 24 Digital input
(1)(2)
Serial clock input
D0/CLKOUT 19 25 Digital IO
(4)
Digital I/O 0 / clock output
D1 20 26 Digital IO
(4)
Digital I/O 1
D2 — 27 Digital IO
(4)
Digital I/O 2
D3 — 28 Digital IO
(4)
Digital I/O 3
(1)
Schmitt-Trigger digital input.
(2)
5V tolerant digital input.
(3)
Leave disconnected if external clock input is applied to XTAL1/CLKIN.
(4)
Schmitt-Trigger digital input when the digital I/O is configured as an input.
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