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**Verilog-Std-1364-2005**是Verilog硬件描述语言的2005年修订版标准，它基于IEEE Std 1364-2001进行更新。Verilog是一种广泛使用的系统级设计语言，特别适用于数字电子系统的建模和仿真。这个标准由IEEE（电气和电子工程师协会）发布，旨在规范和促进电子设计自动化（EDA）领域的设计流程。 **Verilog HDL**是该标准的核心内容，它定义了一种形式化的语言，用于电子系统的全生命周期管理，包括设计、验证、综合、测试以及硬件数据的交流、维护、修改和采购。Verilog具有机器可读和人类可读的特点，使得设计者能够用代码来表示复杂的数字逻辑电路，并且可以通过工具进行自动化处理。 **主要受众**：Verilog-Std-1364-2005标准主要服务于两个群体，一是开发支持Verilog语言的工具制造商，他们需要理解并实现符合标准的编译器、仿真器和其他EDA工具；二是高级语言用户，他们利用Verilog进行系统级和门级的设计与验证。 **功能和应用**： 1. **设计**：Verilog允许设计师用结构化的方式描述电路，包括组合逻辑、时序逻辑、寄存器传输级（RTL）等。 2. **验证**：通过编写测试平台和激励向量，设计师可以模拟电路行为，检查设计的正确性。 3. **综合**：将Verilog代码转化为门级网表，以便进一步进行物理布局和布线。 4. **测试**：在设计的各个阶段，Verilog可以用于生成测试波形，帮助发现和修复设计错误。 5. **数据交换**：Verilog模型可以作为设计文档，方便团队间的合作和知识产权的保护。 **关键词**：计算机语言、硬件描述语言、电子设计自动化、系统级设计、门级设计、设计验证、综合、测试。 **2005年修订版的变化**：2005年的修订可能包含了一些增强和修正，例如对语言规范的改进、新的语法特性、更好的互操作性和一致性，以及对之前版本中已知问题的解决。 Verilog-Std-1364-2005是电子工程和计算机科学领域的一个重要参考标准，它为电子系统的设计提供了标准化的描述手段，推动了整个行业的技术进步和创新。

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IEEE Std 1364™-2005

(Revision of IEEE Std 1364-2001)

IEEE Standard for Verilog

Hardware Description Language

I E E E

3 Park Avenue

New York, NY 10016-5997, USA

7 April 2006

IEEE Computer Society

Sponsored by the

Design Automation Standards Committee

Authorized licensed use limited to: Bucknell University. Downloaded on June 12,2014 at 13:56:54 UTC from IEEE Xplore. Restrictions apply.

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Introduction

The Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-

1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard

textual format for a variety of design tools, including verification simulation, timing analysis, test analysis,

and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice

by an overwhelming number of integrated circuit (IC) designers.

Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,

and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels is

essentially provided by the semantics of two data types: nets and variables. Continuous assignments, in

which expressions of both variables and nets can continuously drive values onto nets, provide the basic

structural construct. Procedural assignments, in which the results of calculations involving variable and net

values can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-

ules, each of which has an input/output (I/O) interface, and a description of its function, which can be struc-

tural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets.

The Verilog language is extensible via the programming language interface (PLI) and the Verilog proce-

dural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to access

information contained in a Verilog HDL description of the design and facilitates dynamic interaction with

simulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulation

and computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, and

annotators.

The language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel Univer-

sity in England under a contract to produce a test generation system for the British Ministry of Defense.

HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verification

simulation, timing analysis, fault simulation, and test generation.

In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent

Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of

Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. In 1993, the first IEEE

working group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard as

IEEE Std 1364-1995.

After the standardization process was complete, the IEEE P1364 Working Group started looking for feed-

back from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. This

led to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001.

With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identify

outstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-

ing on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led to

incompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was estab-

lished as a subcomittee of the SystemVerilog P1800 Working Group to help ensure consistent resolution of

such issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.

This introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog

Hardware Description Language.

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