3
by 0.4, and the C
2
value was typically set as zero. Meanwhile, if the ReLU function was omitted
for the output layer, there would be no C
2
,
and the C
1
value typically amounted to zero. The
threshold Th filtered out the small error values, i.e., |se|<Th, which prevented weight updates
that were extremely sensitive and improved the convergence of the algorithm. Moreover, this
whole STELLAR scheme could be extended to larger neural networks by quantizing the sy
1
and
setting the threshold Th more flexibly.
The effectiveness of the STELLAR architecture does not rely on the specific forms of
neurons and can be applied to various types of activation functions. In this work, the ReLU
activation function was experimentally demonstrated with this fabricated chip because ReLU is
widely adopted in current neural networks. When the neuron functions of the output layer are
configured to sigmoid, tanh, etc., sy
2
will be quantized by the neuron’s corresponding derivative
function, instead of the value of y
2
directly. These only require standard CMOS circuitry
engineering, and different kinds of neurons can be realized easily through lookup table circuits,
and so on.
2. STELLAR update scheme under device asymmetric switching
Practical memristor devices suffer from non-ideal tuning behaviors, such as the nonlinearity
and asymmetry of the updating curves, which hinder the development and exploration of
memristor-based edge learning applications. The STELLAR update method introduced a
threshold-based ternarized scheme to compute the input and output derivative vectors, which
were subsequently used to calculate the sign-based weight gradients. This STELLAR scheme
was beneficial to simplify the hardware design for gradient calculations and weight updates,
saving hardware costs to implement a fully integrated memristor chip for edge learning. More
importantly, this scheme allowed memristor chips to accommodate practical device asymmetric
switching behaviors and to achieve a close approximation to the standard BP rule by omitting
small weight updates with the threshold configurations.
To prove this, we first investigated how different device asymmetry factors affected the
system accuracies. We established a device asymmetric switching model and chose three
representative conductance-modulating curves under the pulse train (fig. S2A). Curve L1
depicted symmetric updating behavior, and curves L2 and L3 represented updating behaviors
with typical and severe asymmetry, respectively. According to the test data, the memristor
conductance could be modulated between 2 and 20 μS under an identical pulse train. Meanwhile,
the model also incorporated device asymmetry under nonlinear conductance modulating
procedure, and the conductance change ΔG regarding conductance state G was modeled and
configured to simulate different memristor programming asymmetry factors. Device state
variations were incorporated as Gaussian noises.
Next, we performed the simulation for MNIST image recognition with a two-layer MLP by
training the weights of the last layer from random initial states. Based on the STELLAR
architecture in Fig. 2A in the main text, we compared the test accuracies between zero-threshold
configuration (i.e., the Manhattan rule or BP-without-verification scheme) and non-zero-
threshold (i.e., the STELLAR scheme) after convergence. The result is illustrated in fig. S2B,
indicating that the accuracies under the zero-threshold configuration were poor. The ideal
behavior with linear and symmetric updating curve resulted in >15% accuracy drop for L1, and
the device updating asymmetries for L2 and L3 led to additional 4% and 24% accuracy drops,
respectively. However, by integrating on-chip learning with the STELLAR tuning scheme, the
