Debugware
User Guide
03/2018
Hercules Microelectronics, Inc.
China
User Guide of Debugware
http://www.hercules-micro.com 1
Contents
Contents ............................................................................................................................................................... 1
1 Introduction .................................................................................................................................................. 2
2 Debugware Overview ................................................................................................................................... 3
2.1 Pin Description ................................................................................................................................. 3
2.2 Block Diagram ................................................................................................................................... 3
3 Debugware IP Usage ..................................................................................................................................... 4
4 Generate File Directory Structure .............................................................................................................. 10
Revision History .................................................................................................................................................. 11
User Guide of Debugware
http://www.hercules-micro.com 2
1 Introduction
This document mainly describes the usage of the debugware IP. The debugware IP is an embedded logic
analyzer to help designer inspect the signal transition inside FPGA. The waveform of sampled signals is stored
in the embedded memory and the data can be retrieved through JTAG port after trigging events happened.
Then, the designers can get a waveform picture according to the conditions configured.
The debugware IP supports the following features:
Trigger condition can be configured dynamically
Support real-time capture
Support trigger type and condition
Arithmetic
equal
not equal
Edge
rise
fall
Support up to 4 LA cores
Multiple LA cores management
Multiple EMB utilized to expand captured data width and depth
M7&M5: data width:2~96 depth:512|1024|2048|4096|8192|16384
HR3&HR2: data width:2~72 depth:512|1024|2048|4096|8192
C1: data width:2~160 depth:512|1024|2048|4096|8192|16384|32768|65536
Note:
Please make sure that the design meets timing requirements.
Do not exceed the total number of EMBs in your design after adding the debugware IP.
Device family support:
HME-M7, HME-M5, HME-HR3, HME-HR2, HME-C1
User Guide of Debugware
http://www.hercules-micro.com 3
2 Debugware Overview
2.1 Pin Description
Table 2-1 debugware interface
Interface
Name
Direction
Width
Description
User
interface
ref_clk_n
(n=0,1,2,3)
Input
1
Input reference clock,
used to sample data
data_in_n
(n=0,1,2,3)
Input
Data Width
Input data used to inspect,
from FPGA
trig_out_n
(n=0,1,2,3)
Output
1
Trigger output, active high,
indicates trigger condition
is met.
2.2 Block Diagram
TAP
LA
Manager
LA Core0
LA Core1
LA Core2
LA Core3
Debugware IP
user logic
Figure 2-1 debugware block diagram
The debugware IP can be divided into three modules: TAP, LA Manager and LA Cores as shown in above
figure.
TAP module is the wrapper logic of debug interface with JTAG controller
LA Manager is the control unit of debugware IP. It is a bridge between TAP and LA Cores. There is only
one LA Manager but it can control up to 4 LA Cores simultaneously.
LA Core is the executive unit in debugware IP. It includes trigger generator module and storage
module.
- 1
- 2
- 3
- 4
前往页