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Timing Diagram of a Load Instruction
Clk
PC
Rs, Rt, Rd,
Op, Func
Clk-to-Q
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busA
Register File Access Time
Old Value New Value
busB
ALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
ExtOp Old Value New Value
ALUSrc Old Value New Value
Address Old Value New Value
busW Old Value New
Delay through Extender & Mux
Data Memory Access Time
Instruction Fetch
Instr Decode /
Reg. Fetch
Address Reg Wr
Data Memory
Register File Write Time
1
3
2
