################################################################################
# Vivado (TM) v2019.1 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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基于FPGA设计的W5500以太网通讯设计
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基于FPGA设计的W5500以太网通讯设计 (589个子文件)
__synthesis_is_complete__ 0B
xsim.ini.bak 26KB
elaborate.bat 1KB
simulate.bat 882B
compile.bat 824B
runme.bat 229B
runme.bat 229B
W5500_top.bit 3.86MB
xsim_1.c 11KB
xsim.dbg 132KB
W5500_top_routed.dcp 672KB
ila_0.dcp 626KB
ila_0.dcp 626KB
W5500_top_placed.dcp 584KB
W5500_top_opt.dcp 409KB
dbg_hub.dcp 348KB
W5500_top.dcp 170KB
blk_mem_gen_0.dcp 114KB
fifo.dcp 81KB
blk_mem_gen_0.dcp 38KB
blk_mem_gen_0.dcp 31KB
blk_mem_gen_0.dcp 31KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 29KB
blk_mem_gen_0.dcp 27KB
blk_mem_gen_0.dcp 27KB
PLL.dcp 9KB
compile.do 781B
compile.do 747B
compile.do 697B
compile.do 683B
simulate.do 341B
simulate.do 340B
simulate.do 340B
elaborate.do 213B
simulate.do 203B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
W5500以太网模块说明.docx 568KB
xsimk.exe 258KB
run.f 524B
run.f 504B
usage_statistics_webtalk.html 41KB
usage_statistics_ext_xsim.html 3KB
hw_ila_data_1.ila 9KB
.xsim_webtallk.info 65B
xsim.ini 26KB
xsim.ini 25KB
xsimSettings.ini 1KB
webtalk_16468.backup.jou 861B
webtalk_14384.backup.jou 861B
webtalk_20788.backup.jou 861B
webtalk_14260.backup.jou 861B
webtalk_6860.backup.jou 860B
webtalk.jou 859B
vivado.jou 715B
vivado.jou 710B
ISEWrap.js 8KB
ISEWrap.js 8KB
rundef.js 1KB
rundef.js 1KB
hw_ila_1.layout 247KB
runme.log 70KB
runme.log 61KB
elaborate.log 2KB
xvlog.log 1KB
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
summary.log 983B
webtalk_14384.backup.log 930B
webtalk_16468.backup.log 930B
webtalk_14260.backup.log 930B
webtalk_20788.backup.log 930B
webtalk_6860.backup.log 929B
webtalk.log 928B
simulate.log 619B
xsimkernel.log 319B
xsimcrash.log 0B
W5500.lpr 343B
xsim.mem 32KB
xsim_0.win64.obj 233KB
xsim_1.win64.obj 8KB
elab.opt 218B
vivado.pb 162KB
vivado.pb 104KB
vivado.pb 52KB
place_design.pb 50KB
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