FAIRCHILD-MLP14D.pdf_MLP封装资源-CSDN文库

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随着电子设备的快速发展，USB接口已成为连接各种设备与计算机之间的桥梁。在这一背景下，FAIRCHILD公司推出了其MLP14D芯片，这是一款具有集成USB通用串行总线传输器和电压调节器功能的电子元件。MLP14D的设计初衷是为便携式电子产品提供一个高效、小尺寸且可靠的USB接口解决方案。 MLP14D芯片的核心优势之一是它遵循USB 2.0规范，这意味着它能够保证与市场上绝大多数USB设备的兼容性。这一特性对于制造商来说极为重要，因为它确保了产品可以在各种不同的USB环境中正常工作。此外，MLP14D提供的电压转换功能，使得依赖于特定供电电压的设备能够与USB标准的物理层进行有效的接口连接。这一转换从标准的5V降至3.3V，适应了更广泛的电源需求。在数据传输效率方面，MLP14D支持高达12Mbits/s的全速传输率，满足了USB 2.0规范对数据传输速率的要求。这一性能保证了设备在高速传输数据时的稳定性和高效性，这对于个人计算机外设、移动电话以及其他需要处理大量数据的设备尤其重要。 MLP14D芯片采用了先进的MLP封装技术，这不仅为其提供了16个终端和HBCC脚印，还显著减小了芯片的体积。这种设计可以提高电路板的空间利用率，为现代便携式设备的紧凑设计提供了技术保障。芯片的小尺寸使得它非常适合于空间有限的移动设备中，如个人数字助理（PDA）、手机、MP3播放器等。为了提高系统的稳定性，FAIRCHILD特别在MLP14D芯片中加入了对D+和D-端口的静电放电（ESD）保护措施。提供高达15kV的人体模型（HBM）ESD保护，这有助于保护USB接口不受静电冲击的损害，从而增强了整个系统的抗干扰能力。此外，Vbusmon终端的加入，使得系统可以实时监控Vbus线路的状态，这对于及时发现并处理USB总线的异常情况至关重要。在订购信息方面，FAIRCHILD提供了两种不同的封装选择，以满足不同制造商的需求。MPXMLP14D采用14端口的MLP封装，尺寸仅为2.5mm正方形，适合大批量生产和自动化装配；而MHXMLP16HB则采用16端口的MHBCC封装，尺寸为3mm正方形，同样适合高密度装配。两种封装都符合无铅（Pb-Free）的JEDEC J-STD-020B标准，这有助于制造商满足环保要求。典型的应用场合包括个人数字助理（PDA）、个人计算机外设、手机、MP3播放器、数码相机以及信息家电等。这些应用场景往往需要小巧、高效、稳定的USB接口解决方案，MLP14D芯片正好满足了这些要求。 FAIRCHILD的MLP14D芯片在设计USB接口设备时提供了诸多优势，包括其遵循USB 2.0规范的高兼容性、高效的电压调节功能、高速的数据传输率、先进的封装技术、强健的ESD保护以及方便的封装选项。这些特性共同为MLP14D芯片在便携式电子产品市场上的广泛应用奠定了坚实的基础，使其成为设计师们在设计USB接口设备时的理想选择，不仅简化了系统设计，而且提升了产品的可靠性和性能。

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USBIT1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator

October 2007

USB1T1103 Rev. 1.0.3

USB1T1103

Universal Serial Bus Peripheral Transceiver

with Voltage Regulator

Features

■ Complies with Universal Serial Bus Specification 2.0

■ Integrated 5V to 3.3V voltage regulator for powering

VBus

■ Utilizes digital inputs and outputs to transmit and

receive USB cable data

■ Supports full speed (12Mbits/s) data rates

■ Ideal for portable electronic devices

■ MLP technology package (16 terminal) with HBCC

footprint

■ 15kV contact HBM ESD protection on bus terminals

■ Supports disable mode and is functionally equivalent

to Philips ISP1102

Applications

■ PDA

■ PC Peripherals

■ Cellular Phones

■ MP3 Players

■ Digital Still Camera

■ Information Appliance

Description

This chip provides a USB Transceiver functionality with a

voltage regulator that is compliant to USB Specification

Rev 2.0. this integrated 5V to 3.3V regulator allows inter-

facing of USB Application specific devices with supply

voltages ranging from 1.65V to 3.6V with the physical

layer of Universal Serial Bus. It is capable of operating at

12Mbits/s (full speed) data rates and hence is fully com-

pliant to USB Specification Rev 2.0. The Vbusmon termi-

nal allows for monitoring the Vbus line.

The USB1T1103 also provides exceptional ESD protec-

tion with 15kV contact HBM on D+,D- terminals

Ordering Information

Pb-Free package per JEDEC J-STD-020B.

Part Number Package

Number

Product code

Top Mark

Pb-Free Package Description Packing

Method

USB1T1103MPX

MLP14D $Y&Z&2&T

USB1103

Yes 14-Terminal Molded Leadless Package

(MLP), 2.5mm Square

3K Units

on Tape

and Reel

USB1T1103MHX

MLP16HB $Y&Z&2&T

USB1103

Yes 16-Terminal Molded Leadless Package

(MHBCC), JEDEC MO-217,3mm

Square

3K Units

on Tape

and Reel

USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator

USB1T1103 Rev. 1.0.3 3

Terminal Descriptions

Terminal

Number

Terminal

Name

I/O Terminal Description

MLP14 MLP16

1 1 OE I Output Enable:

Active LOW enables the transceiver to transmit data on the bus. When not active the transceiver is in

the receive mode (CMOS level is relative to V

CCIO

)

2 2 RCV O Receive Data Output:

Non-inverted CMOS level output for USB differential Input (CMOS output level is relative to V

CCIO

Driven LOW when SUSPN is HIGH; RCV output is stable and preserved during SE0 condition.

33V

I/O Single-ended D+ receiver output V

(CMOS level relative to V

CCIO

Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts

as drive data input V

(see Table 1 and Table 2).

Output drive is 4 mA buffer.

44V

I/O Single-ended D- receiver output V

(CMOS level relative to V

CCIO

Used for external detection of SE0, error conditions, speed of connected device; Terminal also acts

as drive data input V

(see Table 1 and Table 2).

Output drive is 4 mA buffer.

5 5 SUSPND I Suspend:

Enables a low power state (CMOS level is relative to V

CCIO

). While the

SUSPND terminal is active (HIGH) it will drive the RCV terminal to logic “0” state.

— 6 NC No Connect

67V

CCIO

Supply Voltage for digital I/O terminals (1.65V to 3.6V):

When not connected the D+ and D- terminals are in 3-STATE. This supply bus is totally independent

of V

(5V) and V

REG

(3.3V), and must never exceed the V

REG

(3.3) voltage. For V

CCIO

discon-

nected the O+/O- terminals are HIGH Impedance and the V

(3.3V) is turned off.

7 8 Vbusmon O Vbus monitor output (CMOS level relative to V

CCIO

When Vbus > 4.1V then Vbusmon = HIGH and when Vbus < 3.6V then

Vbusmon = LOW. If SUSPND = HIGH then Vbusmon is pulled HIGH.

9, 8 10, 9 D+, D- AI/O Data +, Data -:

Differential data bus conforming to the USB standard. Terminals are HIGH Impedance for bus pow-

ered mode when Vbus < 3.6V. For ByPass Mode then HIGH Impedance when V

REG

/ Vbus < V

REG

minimum.

10 11 NC No Connect

— 12 NC No Connect

11 13 V

REG

(3.3V) Internal Regulator Option:

Regulated supply output voltage (3.0V to 3.6V) during 5V operation;

decoupling capacitor of at least 0.1 µF is required.

Regulator ByPass Option:

Used as supply voltage input for 3.3V operation.

12 14 V

(5.0V) Internal Regulator Option:

Used as supply voltage input (4.0V to 5.5V); can be connected directly to USB line Vbus.

Regulator ByPass Option:

Connected to V

REG

(3.3V)

13 15 V

(3.3V) Pull-up Supply Voltage (3.3V ± 10%):

Connect an external 1.5kΩ resistor on D+ (FS data rate);

Terminal function is controlled by Config input terminal:

Config = LOW - V

(3.3V) is floating (HIGH Impedance) for zero pull-up current.

Config = HIGH - V

(3.3V) = 3.3V; internally connected to V

REG

(3.3V).

is OFF in disable mode.

14 16 Config I USB connect or disconnect software control input.

Configures 3.3V to external 1.5kΩ resistor on D+ when HIGH.

Exposed

Diepad

Exposed

Diepad

GND GND GND supply down bonded to exposed diepad to be connected to the PCB GND.

USB1T1103 Universal Serial Bus Peripheral Transceiver with Voltage Regulator

USB1T1103 Rev. 1.0.3 4

Functional Description

The USB1T1103 transceiver is designed to convert

CMOS data into USB differential bus signal levels and to

convert USB differential bus signal to CMOS data.

To minimize EMI and noise the outputs are edge rate

controlled with the rise and fall times controlled and

defined for full speed data rates only (12Mbits/s). The

rise, fall times are balanced between the differential ter-

minals to minimize skew.

The USB1T1103 differs from earlier USB Transceiver in

that the V

and V

terminals are now I/O termi-

nals rather than discrete input and output terminals.

Table 1 describes the specific terminal functionality

selection. Table 2 and Table 3 describe the specific Truth

Tables for Driver and Receiver operating functions.

The USB1T1103 also has the capability of various power

supply configurations, including a disable mode for

CCIO

disconnected, to support mixed voltage supply

applications (see Table 4) and Section 2.1 for detailed

descriptions.

Functional Tables

Table 1. Function Select

Notes:

1. Signal levels is function of connection and/or pull-up/pull-down resistors.

2. For SUSPND = HIGH mode the differential receiver is inactive and the output RCV is forced LOW. The out-of-suspend signaling

(K) is detected via the single-ended receivers of the V

and V

terminals.

Table 2. Driver Function (OE = L) using Differential Input Interface

Notes:

3. SE0 = Single Ended Zero

Table 3. Receiver Function (OE = H)

Notes:

4. X = Don't Care

5. RCV(0) denotes the signal level on output RCV just prior to the SE0 or SE1 event. This level is stable during the SE0 or SE1

event period.

SUSPND OE D+, D- RCV

Function

L L Driving &

Receiving

Active V

Input V

Input Normal Driving

(Differential Receiver Active)

L H Receiving

(1)

Active V

Output V

Output Receiving

H L Driving Inactive

(2)

Input V

Input Driving during Suspend

(Differential Receiver Inactive)

HH3 STATE

(1)

Inactive

(2)

Output V

Output Low Power State

Data (D+ / D-)

L L SE0

(3)

L H Differential Logic 1

H L Differential Logic 0

H H Illegal State

D+, D- RCV

Differential Logic 1 H H L

Differential Logic 0 L L H

SE0 X L L

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