没有合适的资源?快使用搜索试试~ 我知道了~
adrv9002数据手册
资源推荐
资源详情
资源评论
Data Sheet
ADRV9002
Dual Narrow-Band and Wideband RF Transceiver
Rev. A
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
FEATURES
► 2 × 2 highly integrated transceiver
► Frequency range of 30 MHz to 6000 MHz
► Transmitter and receiver bandwidth from 12 kHz to 40 MHz
► Two fully integrated, fractional-N, RF synthesizers
► LVDS and CMOS synchronous serial data interface options
► Low power monitor and sleep modes
► Multichip synchronization capabilities
► Fast frequency hopping
► Dynamic profile switching for dynamic data rates and sample
rates
► Fully integrated DPD for narrow-band and wideband waveforms
► Fully programmable via a 4-wire SPI
► 12 mm × 12 mm, 196-ball CSP_BGA
APPLICATIONS
► Mission critical communications
► Very high frequency (VHF), ultrahigh frequency (UHF), and cellu-
lar to 6 GHz
► Time division duplexing (TDD) and frequency division duplexing
(FDD) applications
GENERAL DESCRIPTION
The ADRV9002 is a highly integrated RF transceiver that has
dual-channel transmitters, dual-channel receivers, integrated syn-
thesizers, and digital signal processing functions.
The ADRV9002 is a high performance, highly linear, high dynamic
range transceiver designed for performance vs. power consumption
system optimization. The device is configurable and ideally suited
to demanding, low power, portable and battery powered equipment.
The ADRV9002 operates from 30 MHz to 6000 MHz and covers the
UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellu-
lar frequency bands in narrow-band (kHz) and wideband operation
up to 40 MHz. The ADRV9002 is capable of both TDD and FDD
operation.
The transceiver consists of direct conversion signal paths with
state-of-the-art noise figure and linearity. Each complete receiver
and transmitter subsystem includes dc offset correction, quadrature
error correction (QEC), and programmable digital filters, which
eliminate the need for these functions in the digital baseband. In ad-
dition, several auxiliary functions, such as auxiliary analog-to-digital
converters (ADCs), auxiliary digital-to-analog converters (DACs),
and general-purpose inputs/outputs (GPIOs), are integrated to pro-
vide additional monitoring and control capability.
The fully integrated phase-locked loops (PLLs) provide high per-
formance, low power, fractional-N frequency synthesis for the trans-
mitter, receiver, and clock sections. Careful design and layout tech-
niques provide the isolation required in high performance personal
radio applications.
All voltage controlled oscillator (VCO) and loop filter components
are integrated to minimize the external component count. The local
oscillators (LOs) have flexible configuration options and include fast
lock modes.
The transceiver includes low power sleep and monitor modes to
save power and extend the battery life of portable devices while
monitoring communications.
The fully integrated, low power digital predistortion (DPD) is opti-
mized for both narrow-band and wideband signals and enables
linearization of high efficiency power amplifiers.
The ADRV9002 core can be powered directly from 1.0 V, 1.3 V,
and 1.8 V regulators and is controlled via a standard 4-wire serial
port. Other voltage supplies are used to provide proper digital inter-
face levels and to optimize the receiver, transmitter, and auxiliary
converter performance.
High data rate and low data rate interfaces are supported using
configurable CMOS or low voltage differential signaling (LVDS)
serial synchronous interface (SSI) choice.
The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip
scale package ball grid array (CSP_BGA).
Data Sheet ADRV9002
TABLE OF CONTENTS
analog.com Rev. A | 2 of 100
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Functional Block Diagram......................................3
Specifications........................................................ 4
Transmitter Specifications.................................. 4
Receiver Specifications......................................6
Internal LO, External LO, and Device Clock.....13
Digital Interfaces and Auxiliary Converters...... 14
Power Supply Specifications............................15
Current Consumption Estimates (Typical
Values)........................................................... 16
Timing Specifications....................................... 18
Absolute Maximum Ratings.................................21
Reflow Profile................................................... 21
Thermal Resistance......................................... 21
Electrostatic Discharge (ESD) Ratings.............21
ESD Caution.....................................................21
Pin Configuration and Function Descriptions...... 22
Typical Performance Characteristics................... 27
Wideband......................................................... 27
Narrow-Band.................................................... 65
Phase Noise.....................................................90
Theory of Operation.............................................92
Transmitter....................................................... 92
Receiver........................................................... 93
DPD..................................................................94
Clock Input....................................................... 94
Synthesizers.....................................................94
SPI....................................................................95
GPIO Pins........................................................ 95
Auxiliary Converters......................................... 95
JTAG Boundary Scan.......................................96
Applications Information...................................... 97
Power Supply Sequence..................................97
Digital Data Interface........................................97
Outline Dimensions........................................... 100
Ordering Guide...............................................100
REVISION HISTORY
6/2022—Rev. 0 to Rev. A
Changes to Table 2..........................................................................................................................................6
Changes to Frequency Step Parameter and Signal Level Parameter, Table 3..............................................13
Changes to Digital Data Timing (LVDS SSI), Transmitter Data Parameter, Table 12.................................... 18
Change to Table 15........................................................................................................................................21
Changes to Typical Performance Characteristics Section............................................................................. 27
4/2021—Revision 0: Initial Version
Data Sheet ADRV9002
SPECIFICATIONS
analog.com Rev. A | 4 of 100
Electrical characteristics are at the operating ambient temperature range, VDDA_1P0 = 1.0 V, VDDA_1P3 = 1.3 V, VDDA_1P8 = 1.8 V,
VDD_1P0 = 1.0 V, and VDD_1P8 = 1.8 V.
TRANSMITTER SPECIFICATIONS
Table 1. Transmitters (Tx1 and Tx2)
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CENTER FREQUENCY 30 6000 MHz
TRANSMITTER SYNTHESIS
BANDWIDTH
0.012 40 MHz Zero-IF mode, see the DPD section for more information
BANDWIDTH FLATNESS 0.1 dB 10 MHz bandwidth span, including digital compensation
DEVIATION FROM LINEAR PHASE 1 Degrees 40 MHz bandwidth
POWER CONTROL RANGE
In-Phase (I) and Quadrature (Q) Mode 42 dB
Direct Modulation Mode 12 dB
POWER CONTROL RESOLUTION
I and Q Mode 0.05 dB
Direct Modulation Mode 0.5 dB
IN BAND NOISE FLOOR −154 dBFS
1
/Hz 0 dB attenuation, in band noise falls 1 dB for each dB of attenuation for
attenuation settings between 0 dB and 20 dB
OUT OF BAND NOISE FLOOR −156 dBFS/Hz 0 dB attenuation with 3 × bandwidth/2 offset
Tx1 TO Tx2 ISOLATION
30 MHz 98 dB
470 MHz 97 dB
900 MHz 93 dB
2400 MHz 93 dB
3500 MHz 79 dB
5800 MHz 70 dB
IMAGE REJECTION WITH
INITIALIZATION CALIBRATION ONLY
Wideband Up to 20 dB transmitter attenuation, 40 MHz bandwidth, 0 dB observation
receiver attenuation, 18 MHz continuous wave
2
signal input, QEC
3
tracking
calibration is disabled
50 MHz 55 dBc
470 MHz 63 dBc
900 MHz 59 dBc
2400 MHz 60 dBc
3500 MHz 57 dBc
5800 MHz 55 dBc
Narrow-Band Up to 20 dB transmitter attenuation, 25 kHz bandwidth, 0 dB observation
receiver attenuation, 2.1 kHz continuous wave
2
signal input, QEC tracking
calibration is disabled
30 MHz 61 dBc
470 MHz 68 dBc
900 MHz 65 dBc
2400 MHz 60 dBc
3500 MHz 50 dBc
5800 MHz 50 dBc
Data Sheet ADRV9002
SPECIFICATIONS
analog.com Rev. A | 5 of 100
Table 1. Transmitters (Tx1 and Tx2)
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
IMAGE REJECTION WITH
INITIALIZATION CALIBRATION AND
TRACKING CALIBRATION
Wideband 0 dB transmitter attenuation, 40 MHz bandwidth, −0.2 dBFS, 18 MHz
continuous wave
2
signal input, 50 Ω load, 0 dB observation receiver
attenuation, QEC is active
50 MHz 57 dBc
470 MHz 66 dBc
900 MHz 63 dBc
2400 MHz 60 dBc
3500 MHz 61 dBc
5800 MHz 57 dBc
CONTINUOUS WAVE FULL-SCALE
OUTPUT POWER
−0.2 dBFS, 18 MHz continuous wave
2
signal input, 50 Ω load, 0 dB
transmitter attenuation
30 MHz 7.3 dBm
470 MHz 7.3 dBm
900 MHz 7.6 dBm
2400 MHz 7.4 dBm
3500 MHz 7.8 dBm
5800 MHz 7.2 dBm
OUTPUT IMPEDANCE Z
OUT
50 Ω Differential, see the ADRV9001 system development user guide for more
information
MAXIMUM OUTPUT LOAD VOLTAGE
STANDING WAVE RATIO (VSWR)
3 Use the maximum value to ensure adequate calibration
OUTPUT RETURN LOSS Single-ended return loss measured with balun in place on board
30 MHz 17 dB
470 MHz 18 dB
900 MHz 17 dB
2400 MHz 23 dB
3500 MHz 13 dB
5800 MHz 10 dB
OUTPUT THIRD-ORDER INTERCEPT
POINT
0 dB transmitter attenuation, 40 MHz bandwidth, 17 MHz and 18 MHz
continuous wave
2
signal input, digital backoff = 11 dBFS/tone, calibrated at
the device output
Wideband OIP3
WB
50 MHz 31 dBm
470 MHz 31 dBm
900 MHz 30 dBm
2400 MHz 28 dBm
3500 MHz 29 dBm
5800 MHz 27 dBm
Narrow-Band OIP3
NB
0 dB transmitter attenuation, 25 kHz bandwidth, 2.1 kHz and 3.1 kHz
continuous wave
2
signal input, digital backoff = 5 dBFS/tone, calibrated at
the device output
30 MHz 30 dBm
470 MHz 31 dBm
900 MHz 30 dBm
2400 MHz 28 dBm
3500 MHz 27 dBm
5800 MHz 25 dBm
剩余99页未读,继续阅读
资源评论
星空lg
- 粉丝: 2318
- 资源: 16
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- 解析.m3u8文件,合并TS文件生成MP4
- 基于Java语言的Android开发学习笔记设计源码
- 基于多种NLP模型的汉语及英语选词填空设计源码
- 基于Java、HTML、JavaScript、CSS的在线有声读物平台设计源码
- 基于Java语言的StormRealTime电商大数据实时处理设计源码
- 基于SpringBoot和JavaScript的宿舍管理系统设计源码
- 基于Java语言的地质医院后端代码部分sky-take-out设计源码
- 基于JavaScript的简易登记系统设计源码
- 基于Python、CSS、JavaScript、HTML和Shell语言的pgdoc-cn项目设计源码
- 基于Java的科研项目管理设计与实现源码
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功