adrv9002数据手册_ADRV9002发送接口有调时序的回调函数资源-CSDN文库

verilog

97 浏览量 2024-08-23 20:07:42 上传评论收藏 13.44MB PDF 举报

资源推荐

资源详情

资源评论

Data Sheet

ADRV9002

Dual Narrow-Band and Wideband RF Transceiver

Rev. A

DOCUMENT FEEDBACK

TECHNICAL SUPPORT

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to

change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

FEATURES

► 2 × 2 highly integrated transceiver

► Frequency range of 30 MHz to 6000 MHz

► Transmitter and receiver bandwidth from 12 kHz to 40 MHz

► Two fully integrated, fractional-N, RF synthesizers

► LVDS and CMOS synchronous serial data interface options

► Low power monitor and sleep modes

► Multichip synchronization capabilities

► Fast frequency hopping

► Dynamic profile switching for dynamic data rates and sample

rates

► Fully integrated DPD for narrow-band and wideband waveforms

► Fully programmable via a 4-wire SPI

► 12 mm × 12 mm, 196-ball CSP_BGA

APPLICATIONS

► Mission critical communications

► Very high frequency (VHF), ultrahigh frequency (UHF), and cellu-

lar to 6 GHz

► Time division duplexing (TDD) and frequency division duplexing

(FDD) applications

GENERAL DESCRIPTION

The ADRV9002 is a highly integrated RF transceiver that has

dual-channel transmitters, dual-channel receivers, integrated syn-

thesizers, and digital signal processing functions.

The ADRV9002 is a high performance, highly linear, high dynamic

range transceiver designed for performance vs. power consumption

system optimization. The device is configurable and ideally suited

to demanding, low power, portable and battery powered equipment.

The ADRV9002 operates from 30 MHz to 6000 MHz and covers the

UHF, VHF, industrial, scientific, and medical (ISM) bands, and cellu-

lar frequency bands in narrow-band (kHz) and wideband operation

up to 40 MHz. The ADRV9002 is capable of both TDD and FDD

operation.

The transceiver consists of direct conversion signal paths with

state-of-the-art noise figure and linearity. Each complete receiver

and transmitter subsystem includes dc offset correction, quadrature

error correction (QEC), and programmable digital filters, which

eliminate the need for these functions in the digital baseband. In ad-

dition, several auxiliary functions, such as auxiliary analog-to-digital

converters (ADCs), auxiliary digital-to-analog converters (DACs),

and general-purpose inputs/outputs (GPIOs), are integrated to pro-

vide additional monitoring and control capability.

The fully integrated phase-locked loops (PLLs) provide high per-

formance, low power, fractional-N frequency synthesis for the trans-

mitter, receiver, and clock sections. Careful design and layout tech-

niques provide the isolation required in high performance personal

radio applications.

All voltage controlled oscillator (VCO) and loop filter components

are integrated to minimize the external component count. The local

oscillators (LOs) have flexible configuration options and include fast

lock modes.

The transceiver includes low power sleep and monitor modes to

save power and extend the battery life of portable devices while

monitoring communications.

The fully integrated, low power digital predistortion (DPD) is opti-

mized for both narrow-band and wideband signals and enables

linearization of high efficiency power amplifiers.

The ADRV9002 core can be powered directly from 1.0 V, 1.3 V,

and 1.8 V regulators and is controlled via a standard 4-wire serial

port. Other voltage supplies are used to provide proper digital inter-

face levels and to optimize the receiver, transmitter, and auxiliary

converter performance.

High data rate and low data rate interfaces are supported using

configurable CMOS or low voltage differential signaling (LVDS)

serial synchronous interface (SSI) choice.

The ADRV9002 is packaged in a 12 mm × 12 mm, 196-ball chip

scale package ball grid array (CSP_BGA).

Data Sheet ADRV9002

TABLE OF CONTENTS

analog.com Rev. A | 2 of 100

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................3

Specifications........................................................ 4

Transmitter Specifications.................................. 4

Receiver Specifications......................................6

Internal LO, External LO, and Device Clock.....13

Digital Interfaces and Auxiliary Converters...... 14

Power Supply Specifications............................15

Current Consumption Estimates (Typical

Values)........................................................... 16

Timing Specifications....................................... 18

Absolute Maximum Ratings.................................21

Reflow Profile................................................... 21

Thermal Resistance......................................... 21

Electrostatic Discharge (ESD) Ratings.............21

ESD Caution.....................................................21

Pin Configuration and Function Descriptions...... 22

Typical Performance Characteristics................... 27

Wideband......................................................... 27

Narrow-Band.................................................... 65

Phase Noise.....................................................90

Theory of Operation.............................................92

Transmitter....................................................... 92

Receiver........................................................... 93

DPD..................................................................94

Clock Input....................................................... 94

Synthesizers.....................................................94

SPI....................................................................95

GPIO Pins........................................................ 95

Auxiliary Converters......................................... 95

JTAG Boundary Scan.......................................96

Applications Information...................................... 97

Power Supply Sequence..................................97

Digital Data Interface........................................97

Outline Dimensions........................................... 100

Ordering Guide...............................................100

REVISION HISTORY

6/2022—Rev. 0 to Rev. A

Changes to Table 2..........................................................................................................................................6

Changes to Frequency Step Parameter and Signal Level Parameter, Table 3..............................................13

Changes to Digital Data Timing (LVDS SSI), Transmitter Data Parameter, Table 12.................................... 18

Change to Table 15........................................................................................................................................21

Changes to Typical Performance Characteristics Section............................................................................. 27

4/2021—Revision 0: Initial Version