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Next-Generation DRAM 2024 | Report | www.yolegroup.com
GLOSSARY AND DEFINITIONS
1T-1C: DRAM cell with 1 transistor and 1 capacitor
2T-0C: Capacitorless DRAM cell with 2 transistors
ASIC: Application-Specific Integrated Circuit
ASSP: Application-Specific Standard Product
ASP: Average Selling Price
APU: Application Processor Unit
BEOL: Back End of Line
CAGR: Compound Annual Growth Rate
CBA: CMOS Bonded Array
CMOS: Complementary Metal Oxide Semiconductor
CMOX: Conductive Metal-Oxide
CoWoS Chip on Wafer on Substrate
CXL: Compute Express Link
DDR: Double Data Rate
DIMM: Dual In-Line Memory Module
DRAM: Dynamic Random-Access Memory
ECC: Error Code Correction
EUV: Extreme Ultra-Violet
F
2
: Memory-cell size unit (
F
is the smallest feature size)
FC-BGA: Flip Chip Ball Grid Array
FEOL: Front End of Line
FFET: Ferroelectric Field-Effect Transistor
FRAM: Ferroelectric RAM
FOWLP: Fan-Out Wafer-Level Packaging
FPGA: Field-Programmable Gate Array
GDDR: Graphics DDR (used in GPU)
HBM: High Bandwidth Memory
IGZO: Indium Gallium Zinc Oxide
IOPS: Input/Output Operations Per Second
LPDDR: Low-Power DDR (used in mobile applications)
MCP: Multi-Chip Package
MPU: Microprocessor Unit
MRAM: Magnetic Random-Access Memory
NAND: Flash memory with logical NAND-type structure
NOR: Flash memory with logical NOR-type structure
NRAM: Nanotube RAM
NV: Non-Volatile
PCIe: Peripheral Component Interconnect Express
PCM: Phase-Change Memory
PCB: Printed Circuit Board
QLC: Quad-Level Cell
RCD: Register Clock Driver
RRAM: Resistive Random-Access Memory
SAM: Serviceable Available Market
SAQP: Self-Aligned Quadruple Patterning
SADP: Self-Aligned Double Patterning
SAQP: Self-Aligned Quadruple Patterning
SiP: System in Package
SLC: Single-Level Cell
SoC: System on Chip
SRAM: Static Random-Access Memory
SSD: Solid-State Drive
TAM: Total Accessible Market
TSV: Through Silicon Via
WLCSP: Wafer-Level Chip-Scale Packaging
WB-BGA: Wire Bond Ball Grid Array
x, y, z,
α
,
β
,
γ
,
δ: indicate the technology generation in each class, e.g., 1y denotes
the 2
nd
generation of the “10nm class”
