（已读）A Compact Rijndael Hardware Architecture with S-Box Optimiza...
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A Compact Rijndael Hardware Architecture
with S-Box Optimization
Akashi Satoh, Sumio Morioka, Kohji Takano, and Seiji Munetoh
IBM Research, Tokyo Research Laboratory, IBM Japan Ltd., 1623-14,
Shimotsuruma, Yamato-shi, Kanagawa 242-8502, Japan
{akashi,e02716,chano,munetoh}@jp.ibm.com
Abstract. Compact and high-speed hardware architectures and logic
optimization methods for the AES algorithm Rijndael are described.
Encryption and decryption data paths are combined and all arithmetic
components are reused. By introducing a new composite field, the S-Box
structure is also optimized. An extremely small size of 5.4 Kgates is ob-
tained for a 128-bit key Rijndael circuit using a 0.11-µm CMOS standard
cell library. It requires only 0.052 mm
2
of area to support both encryp-
tion and decryption with 311 Mbps throughput. By making effective use
of the SPN parallel feature, the throughput can be boosted up to 2.6
Gbps for a high-speed implementation whose size is 21.3 Kgates.
1 Introduction
DES (Data Encryption Standard) [14,1], which is a common-key block cipher
for US federal information processing standards, has also been used as a de
facto standard for more than 20 years. NIST (National Institute of Standard
Technology) has selected Rijndael [2] as the new Advanced Encryption Standard
(AES) [13]. Many hardware architectures for Rijndael were proposed and their
performances were evaluated by using ASIC libraries [8,18,10,9] and FPGAs [3,
17,6,11,5]. However, they are simple implementations according to the Rijndael
specification, and none are yet small enough for practical use. The AES has to be
embeddable not only in high-end servers but also in low-end consumer products
such as mobile terminals. Therefore, sharing and reusing hardware resources,
and compressing the gate logic are indispensable to produce a small Rijndael
circuit.
The SPN structure of Rijndael is suitable for highly parallel processing, but
it usually requires more hardware resources compared with the Feistel structure
used in many other ciphers developed after DES. This is because, all data is
encoded in each round of Rijndael processing, while only half of data is processed
at once in DES. In addition, Rijndael has two separate data paths for encryption
and decryption.
In this paper, we describe a compact data path architecture for Rijndael,
where the hardware resources are efficiently shared between encryption and de-
cryption. The key arithmetic component S-Box has been implemented using
C. Boyd (Ed.): ASIACRYPT 2001, LNCS 2248, pp. 239–254, 2001.
c
Springer-Verlag Berlin Heidelberg 2001
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