I2C Slave to SPI Master Bridge
Reference Design
FPGA-RD-02111-1.2
December 2019
I2C Slave to SPI Master Bridge
Reference Design
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-RD-02111-1.2
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I2C Slave to SPI Master Bridge
Reference Design
© 2010-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-RD-02111-1.2 3
Contents
1. Introduction .................................................................................................................................................................. 4
2. Features ........................................................................................................................................................................ 4
3. Functional Description .................................................................................................................................................. 4
4. Design Module Description .......................................................................................................................................... 5
4.1. I
2
C Slave Interface ............................................................................................................................................... 5
4.2. I
2
C Data Bus Transaction ..................................................................................................................................... 5
4.3. SPI Read and Write .............................................................................................................................................. 7
5. Test Bench Description ................................................................................................................................................. 8
6. Implementation .......................................................................................................................................................... 10
Technical Support Assistance ............................................................................................................................................. 11
Revision History .................................................................................................................................................................. 12
Figures
Figure 3.1. I
2
C Slave to SPI Master Bridge Block Diagram ..................................................................................................... 4
Figure 4.1. I
2
C Slave Address ................................................................................................................................................. 5
Figure 4.2. Data Format During an I
2
C Master Write Transmission ...................................................................................... 5
Figure 4.3. Configure SPI Master Interface Operation ......................................................................................................... 6
Figure 4.4. I
2
C Master Write Data ......................................................................................................................................... 6
Figure 4.5. I
2
C Master Clear Interrupt .................................................................................................................................. 7
Figure 4.6. I
2
C Master Read Data .......................................................................................................................................... 7
Figure 4.7. I
2
C Master Write Data ......................................................................................................................................... 7
Figure 4.8. Data Appears on the MOSI_MASTER Pin ............................................................................................................ 8
Figure 5.1. I
2
C Master Sends Configure SPI Master Interface Command ............................................................................. 8
Figure 5.2. I
2
C Master Issues STOP, Data Transfer on SPI Bus .............................................................................................. 8
Figure 5.3. I
2
C Master Clear Interrupt .................................................................................................................................. 9
Figure 5.4. I
2
C Master Read Data .......................................................................................................................................... 9
Tables
Table 3.1. I
2
C Slave to SPI Master Bridge Design Signal Descriptions ................................................................................... 5
Table 4.1. Command Functions ............................................................................................................................................ 6
Table 4.2. Bit Allocation of Configuration Data Byte ............................................................................................................ 6
Table 4.3. Parameters I2C_SLAVE_ADDRESS and CLCOK_SEL .............................................................................................. 8
Table 6.1. Performance and Resource Utilization .............................................................................................................. 10
I2C Slave to SPI Master Bridge
Reference Design
© 2010-2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-RD-02111-1.2
1. Introduction
I
2
C and SPI are the two widely-used bus protocols in today’s embedded systems. The I
2
C bus has a minimum pin count
requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with
performance in MHz range. As embedded systems are required to support an increasing number of protocols and
interfaces, bridge designs targeting popular protocols provide solutions to reduce development time and cost. This
reference design implements an I
2
C slave to SPI master bridge. It serves as an interface between the standard I
2
C bus of
a microcontroller and a SPI bus. This allows the microcontroller to communicate directly with the SPI bus through its I
2
C
bus.
2. Features
The I2C Slave to SPI Master Bridge design includes the features listed below:
II2C bus slave interface
Configurable 7-bit I2C slave addressing mode
128-byte data buffer
SPI master interface supporting SPI clocking modes 0, 1, 2, 3
Configurable SPI serial clock (SCLK) frequency
Up to five SPI slave select outputs
Active low interrupt output
3. Functional Description
The functional block diagram of the I
2
C Slave to SPI Master Bridge design is shown in Figure 3.1. This design operates as
an I
2
C slave and an SPI master. It receives commands from the I
2
C master and writes or reads data to and from the SPI
slave, depending on the command received.
scl_in
sda
clk
I
2
C Slave
Interface
Data
Buffer
I
2
C to SPI Bridge
SPI Master
Interface
XRESET
SCLK_MASTER
MOSI_MASTER
SS_N_MASTER_0
SS_N_MASTER_1
SS_N_MASTER_2
SS_N_MASTER_3
SS_N_MASTER_4
MISO_MASTER
intn
Figure 3.1. I
2
C Slave to SPI Master Bridge Block Diagram
