//============================================================================
//
// (C) COPYRIGHT 2001-2008 SYNOPSYS, INC.
// ALL RIGHTS RESERVED
//
// This software and the associated documentation are confidential and
// proprietary to Synopsys, Inc. Your use or disclosure of this
// software is subject to the terms and conditions of a written
// license agreement between you, or your company, and Synopsys, Inc.
//
// The entire notice above must be reproduced on all authorized copies
//
// : //dwh/DW_ocb/DW_memctl/main/bin/ParamsParser.pl
/ : #3
/
// Abstract : DW_memctl, synchronous write, and asynchronous read FIFO.
// combinational flags and read-data.
//
//============================================================================
# Power-on Reset Register Values For Your Configuration
# The "initialize" bit-0 of SDRAM Control Register(SCTLR), on power-on
# will be set to "1" and after auto initialization sequence completion
# will get reset to 0"
Relative Address 0x00: SCONR = 32'h1c3168
Relative Address 0x04: STMG0R = 32'h7a666496
Relative Address 0x08: STMG1R = 32'h70008
Relative Address 0x0C: SCTLR = 32'h3089
Relative Address 0x10: SREFR = 32'h410
Relative Address 0x14: SCSLR0_LOW = 32'h80000000
Relative Address 0x18: SCSLR1_LOW = 32'h10000000
Relative Address 0x1C: SCSLR2_LOW = 32'h20000000
Relative Address 0x20: SCSLR3_LOW = 32'h30000000
Relative Address 0x24: SCSLR4_LOW = 32'h40000000
Relative Address 0x28: SCSLR5_LOW = 32'h50000000
Relative Address 0x2C: SCSLR6_LOW = 32'h60000000
Relative Address 0x30: SCSLR7_LOW = 32'h70000000
Relative Address 0x54: SMSKR0 = 32'h823
Relative Address 0x58: SMSKR1 = 32'h80c
Relative Address 0x5C: SMSKR2 = 32'h25
Relative Address 0x60: SMSKR3 = 32'h44a
Relative Address 0x64: SMSKR4 = 32'h84a
Relative Address 0x68: SMSKR5 = 32'h401
Relative Address 0x6C: SMSKR6 = 32'h401
Relative Address 0x70: SMSKR7 = 32'h401
Relative Address 0x74: CSALIAS0_LOW = 32'h80000000
Relative Address 0x78: CSALIAS1_LOW = 32'h18000000
Relative Address 0x84: CSREMAP0_LOW = 32'h80000000
Relative Address 0x88: CSREMAP1_LOW = 32'h12000000
Relative Address 0x94: SMTMGR_SET0 = 32'h10541
Relative Address 0x98: SMTMGR_SET1 = 32'h1c194f
Relative Address 0x9C: SMTMGR_SET2 = 32'h190942
Relative Address 0xA0: FLASH_TRPDR = 32'hc8
Relative Address 0xA4: SMCTLR = 32'h2480
Relative Address 0xA8: SYNC_FLASH_OPCODE = 32'h0
Relative Address 0xAC: ETN_MODE_REG = 32'h0
Relative Address 0xB0: SFCONR = 32'h22d
Relative Address 0xB4: SFCTLR = 32'h10
Relative Address 0xB8: SFTMGR = 32'h252
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memctrl32.zip
共24个文件
v:20个
txt:1个
tb_params:1个
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2020-08-12
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能够将SRAM存储器挂载到32位AHB总线,实现CPU、DMA等模块,对任意大小的SRAM的读写访问控制。
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memctrl32.zip (24个子文件)
DW_memctrl32
DW_memctl_miu_addrdec.v 35KB
DW_memctl_miu.v 55KB
DW_memctl_bcm01.v 1KB
DW_memctl_hiu_afifo.v 11KB
DW_memctl_miu_smcr.v 47KB
DW_memctl_miu_smc.v 130KB
DW_memctl_hiu_dfifo.v 9KB
README.src 10KB
.tb_params 1KB
DW_memctl_miu_cr.v 166KB
DW_memctl_bcm_params.v 1KB
DW_memctl_params2.v 87KB
DW_memctl.v 21KB
DW_memctl_hiu.v 12KB
DW_memctl.lst 905B
Poweron_Reset_Register_Values.txt 3KB
DW_memctl_fifo.v 5KB
DW_memctl_hiu_dcore.v 10KB
DW_memctl_miu_dmc.v 8KB
DW_memctl_hiu_ctl.v 54KB
DW_memctl_hiu_rbuf.v 8KB
DW_memctl_undef.v 24KB
DW_memctl_hiu_acore.v 10KB
DW_memctl_constants2.v 5KB
共 24 条
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