基于macb改的linux系统4.14内核 MAC层网卡直连（省略硬件phy及驱动）

/* * Cadence MACB/GEM Ethernet Controller driver * * Copyright (C) 2004-2006 Atmel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <linux/clk.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/kernel.h> #include <linux/types.h> #include <linux/circ_buf.h> #include <linux/slab.h> #include <linux/init.h> #include <linux/io.h> #include <linux/gpio.h> #include <linux/gpio/consumer.h> #include <linux/interrupt.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/dma-mapping.h> #include <linux/platform_data/macb.h> #include <linux/platform_device.h> #include <linux/phy.h> #include <linux/of.h> #include <linux/of_device.h> #include <linux/of_gpio.h> #include <linux/of_mdio.h> #include <linux/of_net.h> #include <linux/ip.h> #include <linux/udp.h> #include <linux/tcp.h> #include <linux/pm_runtime.h> #include <linux/crc32.h> #include <linux/inetdevice.h> #include "macb.h" #define MACB_RX_BUFFER_SIZE 128 #define RX_BUFFER_MULTIPLE 64 /* bytes */ #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */ #define MIN_RX_RING_SIZE 64 #define MAX_RX_RING_SIZE 8192 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ * (bp)->rx_ring_size) #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */ #define MIN_TX_RING_SIZE 64 #define MAX_TX_RING_SIZE 4096 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \ * (bp)->tx_ring_size) /* level of occupied TX descriptors under which we wake up TX process */ #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4) #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ | MACB_BIT(ISR_ROVR)) #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \ | MACB_BIT(ISR_RLE) \ | MACB_BIT(TXERR)) #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP)) /* Max length of transmit frame must be a multiple of 8 bytes */ #define MACB_TX_LEN_ALIGN 8 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1))) #define GEM_MTU_MIN_SIZE ETH_MIN_MTU #define MACB_NETIF_LSO NETIF_F_TSO /* Graceful stop timeouts in us. We should allow up to * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions) */ #define MACB_HALT_TIMEOUT 1230 #define MACB_PM_TIMEOUT 100 /* ms */ /* DMA buffer descriptor might be different size * depends on hardware configuration: * * 1. dma address width 32 bits: * word 1: 32 bit address of Data Buffer * word 2: control * * 2. dma address width 64 bits: * word 1: 32 bit address of Data Buffer * word 2: control * word 3: upper 32 bit address of Data Buffer * word 4: unused * * 3. dma address width 32 bits with hardware timestamping: * word 1: 32 bit address of Data Buffer * word 2: control * word 3: timestamp word 1 * word 4: timestamp word 2 * * 4. dma address width 64 bits with hardware timestamping: * word 1: 32 bit address of Data Buffer * word 2: control * word 3: upper 32 bit address of Data Buffer * word 4: unused * word 5: timestamp word 1 * word 6: timestamp word 2 */ static unsigned int macb_dma_desc_get_size(struct macb *bp) { #ifdef MACB_EXT_DESC unsigned int desc_size; switch (bp->hw_dma_cap) { case HW_DMA_CAP_64B: desc_size = sizeof(struct macb_dma_desc) + sizeof(struct macb_dma_desc_64); break; case HW_DMA_CAP_PTP: desc_size = sizeof(struct macb_dma_desc) + sizeof(struct macb_dma_desc_ptp); break; case HW_DMA_CAP_64B_PTP: desc_size = sizeof(struct macb_dma_desc) + sizeof(struct macb_dma_desc_64) + sizeof(struct macb_dma_desc_ptp); break; default: desc_size = sizeof(struct macb_dma_desc); } return desc_size; #endif return sizeof(struct macb_dma_desc); } static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx) { #ifdef MACB_EXT_DESC switch (bp->hw_dma_cap) { case HW_DMA_CAP_64B: case HW_DMA_CAP_PTP: desc_idx <<= 1; break; case HW_DMA_CAP_64B_PTP: desc_idx *= 3; break; default: break; } #endif return desc_idx; } #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc) { if (bp->hw_dma_cap & HW_DMA_CAP_64B) return (struct macb_dma_desc_64 *)((void *)desc + sizeof(struct macb_dma_desc)); return NULL; } #endif /* Ring buffer accessors */ static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index) { return index & (bp->tx_ring_size - 1); } static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue, unsigned int index) { index = macb_tx_ring_wrap(queue->bp, index); index = macb_adj_dma_desc_idx(queue->bp, index); return &queue->tx_ring[index]; } static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue, unsigned int index) { return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)]; } static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index) { dma_addr_t offset; offset = macb_tx_ring_wrap(queue->bp, index) * macb_dma_desc_get_size(queue->bp); return queue->tx_ring_dma + offset; } static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index) { return index & (bp->rx_ring_size - 1); } static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index) { index = macb_rx_ring_wrap(bp, index); index = macb_adj_dma_desc_idx(bp, index); return &bp->rx_ring[index]; } static void *macb_rx_buffer(struct macb *bp, unsigned int index) { return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(bp, index); } /* I/O accessors */ static u32 hw_readl_native(struct macb *bp, int offset) { return __raw_readl(bp->regs + offset); } static void hw_writel_native(struct macb *bp, int offset, u32 value) { __raw_writel(value, bp->regs + offset); } static u32 hw_readl(struct macb *bp, int offset) { return readl_relaxed(bp->regs + offset); } static void hw_writel(struct macb *bp, int offset, u32 value) { writel_relaxed(value, bp->regs + offset); } /* Find the CPU endianness by using the loopback bit of NCR register. When the * CPU is in big endian we need to program swapped mode for management * descriptor access. */ static bool hw_is_native_io(void __iomem *addr) { u32 value = MACB_BIT(LLB); __raw_writel(value, addr + MACB_NCR); value = __raw_readl(addr + MACB_NCR); /* Write 0 back to disable everything */ __raw_writel(0, addr + MACB_NCR); return value == MACB_BIT(LLB); } static bool hw_is_gem(void __iomem *addr, bool native_io) { u32 id; if (native_io) id = __raw_readl(addr + MACB_MID); else id = readl_relaxed(addr + MACB_MID); return MACB_BFEXT(IDNUM, id) >= 0x2; } static void macb_set_hwaddr(struct macb *bp) { u32 bottom; u16 top; bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr)); macb_or_gem_writel(bp, SA1B, bottom); top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4))); macb_or_gem_writel(bp, SA1T, top); gem_writel(bp, RXPTPUNI, bottom); gem_writel(bp, TXPTPUNI, bottom); /* Clear unused address register sets */ macb_or_gem_writel(bp, SA2B, 0); macb_or_gem_writel(bp, SA2T, 0); macb_or_gem_writel(bp, SA3B, 0); macb_or_gem_writel(bp, SA3T, 0); macb_or_gem_writel(bp, SA4B, 0); macb_or_gem_writel(bp, SA4T, 0); } static void macb_get_hwaddr(struct macb *bp) { struct macb_platform_data *pdata; u32 bottom; u16 top; u8 addr[6]; int i; pdata = dev_get_platdata(&bp->pdev->dev); /* Check all 4 address register for valid address */ for (i = 0; i < 4; i++) { bottom = macb_or_gem_readl(bp, SA1B + i * 8); top = macb_or_gem_readl(bp, SA1T + i * 8); if (pdata && pdata->rev_eth_addr) { addr[5] = bottom & 0xff; addr[4] = (bottom >> 8) & 0xff; addr