适用于ccs的程序模板

// TI File $Revision: /main/2 $ // Checkin $Date: April 4, 2007 14:25:21 $ //########################################################################### // // FILE: DSP2833x_SWPrioritizedIsrLevels.h // // TITLE: DSP28 Devices Software Prioritized Interrupt Service Routine // Level definitions. // //########################################################################### // $TI Release: DSP2833x Header Files V1.01 $ // $Release Date: September 26, 2007 $ //########################################################################### #ifndef DSP2833x_SW_PRIORITZIED_ISR_H #define DSP2833x_SW_PRIORITZIED_ISR_H #ifdef __cplusplus extern "C" { #endif //------------------------------------------------------------------------------- // Interrupt Enable Register Allocation For 2833x Devices: //------------------------------------------------------------------------------- // Interrupts can be enabled/disabled using the CPU interrupt enable register // (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). //------------------------------------------------------------------------------- //------------------------------------------------------------------------------- // Set "Global" Interrupt Priority Level (IER register): //------------------------------------------------------------------------------- // The user must set the appropriate priority level for each of the CPU // interrupts. This is termed as the "global" priority. The priority level // must be a number between 1 (highest) to 16 (lowest). A value of 0 must // be entered for reserved interrupts or interrupts that are not used. This // will also reduce code size by not including ISR's that are not used. // // Note: The priority levels below are used to calculate the IER register // interrupt masks MINT1 to MINT16. // // // Note: The priority levels shown here may not make sense in a // real application. This is for demonstration purposes only!!! // // The user should change these to values that make sense for // their application. // // 0 = not used // 1 = highest priority // ... // 16 = lowest priority #define INT1PL 2 // Group1 Interrupts (PIEIER1) #define INT2PL 1 // Group2 Interrupts (PIEIER2) #define INT3PL 4 // Group3 Interrupts (PIEIER3) #define INT4PL 2 // Group4 Interrupts (PIEIER4) #define INT5PL 2 // Group5 Interrupts (PIEIER5) #define INT6PL 3 // Group6 Interrupts (PIEIER6) #define INT7PL 0 // reserved #define INT8PL 0 // reserved #define INT9PL 3 // Group9 Interrupts (PIEIER9) #define INT10PL 0 // reserved #define INT11PL 0 // reserved #define INT12PL 0 // reserved #define INT13PL 4 // XINT13 #define INT14PL 4 // INT14 (TINT2) #define INT15PL 4 // DATALOG #define INT16PL 4 // RTOSINT //------------------------------------------------------------------------------- // Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): //------------------------------------------------------------------------------- // The user must set the appropriate priority level for each of the PIE // interrupts. This is termed as the "group" priority. The priority level // must be a number between 1 (highest) to 8 (lowest). A value of 0 must // be entered for reserved interrupts or interrupts that are not used. This // will also reduce code size by not including ISR's that are not used: // // Note: The priority levels below are used to calculate the following // PIEIER register interrupt masks: // MG11 to MG18 // MG21 to MG28 // MG31 to MG38 // MG41 to MG48 // MG51 to MG58 // MG61 to MG68 // MG71 to MG78 // MG81 to MG88 // MG91 to MG98 // MG101 to MG108 // MG111 to MG118 // MG121 to MG128 // // Note: The priority levels shown here may not make sense in a // real application. This is for demonstration purposes only!!! // // The user should change these to values that make sense for // their application. // // 0 = not used // 1 = highest priority // ... // 8 = lowest priority // #define G11PL 7 // SEQ1INT (ADC) #define G12PL 6 // SEQ2INT (ADC) #define G13PL 0 // reserved #define G14PL 1 // XINT1 (External) #define G15PL 3 // XINT2 (External) #define G16PL 2 // ADCINT (ADC) #define G17PL 1 // TINT0 (CPU Timer 0) #define G18PL 5 // WAKEINT (WD/LPM) #define G21PL 4 // EPWM1_TZINT (ePWM1 Trip) #define G22PL 3 // EPWM2_TZINT (ePWM2 Trip) #define G23PL 2 // EPWM3_TZINT (ePWM3 Trip) #define G24PL 1 // EPWM4_TZINT (ePWM4 Trip) #define G25PL 5 // EPWM5_TZINT (ePWM5 Trip) #define G26PL 6 // EPWM6_TZINT (ePWM6 Trip) #define G27PL 0 // reserved #define G28PL 0 // reserved #define G31PL 4 // EPWM1_INT (ePWM1 Int) #define G32PL 1 // EPWM2_INT (ePWM2 Int) #define G33PL 1 // EPWM3_INT (ePWM3 Int) #define G34PL 2 // EPWM4_INT (ePWM4 Int) #define G35PL 2 // EPWM5_INT (ePWM5 Int) #define G36PL 1 // EPWM6_INT (ePWM6 Int) #define G37PL 0 // reserved #define G38PL 0 // reserved #define G41PL 2 // ECAP1_INT (eCAP1 Int) #define G42PL 1 // ECAP2_INT (eCAP2 Int) #define G43PL 3 // ECAP3_INT (eCAP3 Int) #define G44PL 3 // ECAP4_INT (eCAP4 Int) #define G45PL 5 // ECAP5_INT (eCAP5 Int) #define G46PL 5 // ECAP6_INT (eCAP6 Int) #define G47PL 0 // reserved #define G48PL 0 // reserved #define G51PL 2 // EQEP1_INT (eQEP1 Int) #define G52PL 1 // EQEP2_INT (eQEP2 Int) #define G53PL 0 // reserved #define G54PL 0 // reserved #define G55PL 0 // reserved #define G56PL 0 // reserved #define G57PL 0 // reserved #define G58PL 0 // reserved #define G61PL 3 // SPIRXINTA (SPI-A) #define G62PL 1 // SPITXINTA (SPI-A) #define G63PL 4 // MRINTB (McBSP-B) #define G64PL 6 // MXINTB (McBSP-B) #define G65PL 2 // MRINTA (McBSP-A) #define G66PL 1 // MXINTA (McBSP-A) #define G67PL 0 // reserved #define G68PL 0 // reserved #define G71PL 5 // DINTCH1 (DMA) #define G72PL 4 // DINTCH2 (DMA) #define G73PL 4 // DINTCH3 (DMA) #define G74PL 2 // DINTCH4 (DMA) #define G75PL 3 // DINTCH5 (DMA) #define G76PL 1 // DINTCH6 (DMA) #define G77PL 0 // reserved #define G78PL 0 // reserved #define G81PL 1 // I2CINT1A (I2C-A) #define G82PL 2 // I2CINT2A (I2C-A) #define G83PL 0 // reserved #define G84PL 0 // reserved #define G85PL 4 // SCIRXINTC (SCI-C) #define G86PL 3 // SCITXINTC (SCI-C) #define G87PL 0 // reserved #define G88PL 0 // reserved #define G91PL 1 // SCIRXINTA (SCI-A) #define G92PL 5 // SCITXINTA