Serial RapidIO Gen2
Endpoint v4.1
LogiCORE IP Product Guide
Vivado Design Suite
PG007 June 7, 2017
北京恒润科技 CE 射频仿真 左吁文
Serial RapidIO Gen2 v4.1
PG007 June 7, 2017
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Table of Contents
IP Facts
Chapter 1: Overview
System Overview
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5
Applications
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7
Unsupported Features
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7
Licensing
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7
Recommended Design Experience
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8
Chapter 2: Product Specification
Standards Compliance
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9
Performance
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10
Resource Utilization
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Serial Transceiver Support.
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Top-Level Wrapper
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11
Port Descriptions
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Register Space
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Chapter 3: Designing with the Core
General Design Guidelines
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73
Clocking
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Resets
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Shared Logic Related Port Descriptions
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Protocol Description
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102
Chapter 4: Design Flow Steps
Customizing and Generating the Core
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129
Constraining the Core
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149
Simulation
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152
Synthesis and Implementation
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152
Chapter 5: Detailed Example Design
Overview
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153
Serial RapidIO Gen2 v4.1
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Generating the Core
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153
Directory and File Contents
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154
Example Design
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157
Implementing the Example Design
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162
Simulating the Example Design
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162
Chapter 6: Test Bench
Demonstration Test Bench
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165
Appendix A: Packet and Control Symbol Formats
Scope
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167
Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite
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170
Upgrading in the Vivado Design Suite
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170
Appendix C: Debugging
Finding Help on Xilinx.com
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178
Debug Tools
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Waveform Analysis and Debug
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180
Hardware Debug
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189
Appendix D: Additional Resources and Legal Notices
Xilinx Resources
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195
References
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195
Revision History
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196
Please Read: Important Legal Notices
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197
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Introduction
LogiCORE™IP 串行 RapidIO Gen2 端点解决方案
（SRIO Gen2 端点）包括高度灵活和优化的串行
RapidIO Gen2 物理层和串行 RapidIO Gen2 逻辑
（I / O）和传输层。该 IP 解决方案以网表形式提
供，带有支持示例设计代码。 SRIO Gen2 端点支
持 1x，2x 和 4x 通道宽度。它配备了可配置的缓
冲设计，参考时钟模块，复位模块和配置结构参
考设计。 SRIO Gen2 端点使用 AXI4-Stream 接
口进行高吞吐量数据传输，使用 AXI4-Lite 接口
进行配置（维护）接口 .
Features
•
专为 RapidIO 互连规范而设计 rev.
2.2
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支持 1x，2x 和 4x 操作，能够从 2x 或 4x
训练低至 1x
•
支持每车道速度 1.25,2.5,3.125,5.0 和
6.25 Gbaud
Logical Layer
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并发启动器和目标操作
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门铃和消息支持
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维护发送的专用端口
•
使用标准 AXI4-Lite 和 AXI4-
Stream 接口控制数据流的简单握
手机制
•
所有传出数据包上的可编程源 ID
•
可选的大型系统支持 16 位设备 ID
IP Facts
Buffer
•
独立配置的 TX 和 RX 缓冲区深度为 8,16 或
32 个数据包
•
支持独立时钟
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可选的 TX 流量控制支持
Physical Layer
•
可配置的 IDLE1 / IDLE2 序列支持
•
支持关键请求流程
•
支持多播事件
LogiCORE IP Facts Table
Core Specifics
支持的设备系
列（1）
UltraScale+™ Families,
UltraScale™ Architecture, Zynq®-7000,
Virtex®-7, Kintex®-7, Artix®-7
支持的用户
界面
AXI4-Stream, AXI4-Lite
资源
Performance and Resource Utilizationweb
page
Provided with Core
设计文件
Encrypted RTL
示例设计
Configuration Fabric Design
with Verilog Source
Test Bench
Verilog
Constraints File
XDC
Simulation Model
Encrypted Verilog
支持的
S / W
驱动程序
N/A
Tested Design Flows
(2)
Design Entry
Vivado® Design Suite
Simulation
(3)
For the supported simulators, see the Xilinx
Design Tools: Release Notes Guide
Synthesis
Vivado synthesis
Support
Provided by Xilinx at the Xilinx Support web page
1.
For a complete list of supported devices, see the Vivado IP
catalog.
2.
For the supported versions of the tools, see the
Xilinx Design Tools: Release NotesGuide.
3.
Requires a Verilog LRM-IEEE 1364-2005 encryption-compliant
simulator.
Serial RapidIO Gen2 v4.1 www.xilinx.com 4
PG007 June 7, 2017 Product Specification
Serial RapidIO Gen2 v4.1
PG007 June 7, 2017
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Chapter 1
Overview
RapidIO 互连架构旨在与最流行的集成通信处理器，主机处理器和网络数字信号处理器兼容，
是一种高性能的分组交换互连技术。它满足了高性能嵌入式行业对系统内互连中可靠性，增加
的带宽和更快的总线速度的需求.
RapidIO 标准分为三层：逻辑，传输和物理。逻辑层定义整体协议和数据包格式。这是端点启动
和完成事务所必需的信息。传输层提供数据包从端点移动到端点所需的路由信息 。物理层描
述了设备级接口细节，例如数据包传输机制，流控制，电气特性和低级错误管理。此分区提供了
将新事务类型添加到逻辑规范的灵活性，而无需修改传输或物理层规范.
•
For more information about the RapidIO core, see www.xilinx.com/rapidio
•
For more information about the RapidIO standards and specifications, see
www.rapidio.org
System Overview
SRIO Gen2 端点包含以下内容:
•
串行 RapidIO Gen2 顶级包装器（srio_gen2_ <core_version> _unifiedtop）包含:
°
Serial RapidIO Gen2 Physical Layer (PHY)
°
Serial RapidIO Gen2 Logical (I/O) and Transport Layer (LOG)
°
Serial RapidIO Gen2 Buffer Design (BUF)
•
时钟，复位和配置访问的参考设计
SRIO Gen2 端点如图 1-1 所示.
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