HDMI_HDMI_verilog_DVI_

******************************************************************************* ** 2006-2008 Xilinx, Inc. All Rights Reserved. ** Confidential and proprietary information of Xilinx, Inc. ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: ** / / Date Last Modified: ** /___/ /\ Date Created: ** \ \ / \ ** \___\/\___\ ** ** Device: Spartan-3A, Spartan-3AN and Spartan-3ADSP ** Purpose: ** Reference: XAPP460 Video Connectivity Using TMDS I/O in Spartan-3A FPGAs ** Revision History: ** ******************************************************************************* ** ** Disclaimer: ** ** Xilinx licenses this Design to you "AS-IS" with no warranty of any kind. ** Xilinx does not warrant that the functions contained in the Design will ** meet your requirements,that the Design will operate uninterrupted or be ** error-free, or that errors or bugs in the Design will be corrected. ** Xilinx makes no warranties or representations in regard to the results ** obtained from your use of the Design with respect to accuracy, reliability, ** or otherwise. ** ** XILINX MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS OR IMPLIED, ** STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES ** OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. ** IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR FOR ** ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING FROM ** YOUR USE OF THIS DESIGN. ******************************************************************************* This readme describes how to use the files that come with XAPP460. ******************************************************************************* ** IMPORTANT NOTES ** 1) All design files have been hardware tested using a Xilinx internal TMDS characterization board. ******************************************************************************** To incorporate the insert name here module into an ISE design project: Verilog flow: 1) Create an ISE project using appropriate design files discussed in the xapp460.pdf. 2) Create a Xilinx UCF file as discussed in the xapp460.pdf.