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DACx050 1 +

VREFIO

Bipolar

Output

Signal

Input

Signal

Output

Serial

Interface

OPAMP

VOUT

DAC

Buffer

BUF

Power Down Logic

Resistive Network

Interface Logi c

Power On Reset

VREFIO

SCLK or SCL

SDIN or SDA

SYNC

AGND

VDD

DAC

Internal

Reference

SPI2C

or A0

Product

Folder

Order

Now

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DAC80501

DAC70501

DAC60501

SBAS794D –NOVEMBER 2018–REVISED FEBRUARY 2020

DACx0501 16-Bit, 14-Bit, and 12-Bit, 1-LSB INL, Voltage-Output DACs

With Precision Internal Reference

1 Features

• 16-bit performance: 1-LSB INL and DNL (max)

• Low glitch energy: 4 nV–s

• Wide power supply: 2.7 V to 5.5 V

• Buffered output range: 5 V, 2.5 V, or 1.25 V

• Very-low power: 1 mA at 5.5 V

• Integrated 5-ppm/˚C (max), 2.5-V precision

reference

• Pin-selectable serial interface:

– 3-wire, SPI compatible up to 50-MHz

– 2-wire, I

C compatible

• Power-on-reset: Zero scale or midscale

• 1.62-V VIH with VDD = 5.5 V

• Temperature range: –40˚C to +125˚C

• Packages: Small 8-Pin WSON and 10-Pin VSSOP

2 Applications

• Oscilloscope (DSO)

• Semiconductor test

• Data acquisition (DAQ)

• LCD test

• Small cell base station

• Analog output module

• Process analytics (pH, gas, concentration, force

and humidity)

• DC power supply, ac source, electronic load

3 Description

The 16-bit DAC80501, 14-bit DAC70501, and 12-bit

DAC60501 (DACx0501) digital-to-analog converters

(DACs) are highly accurate, low-power devices with

voltage-output. The DACx0501 are specified

monotonic by design, and offer linearity of < 1 LSB.

These devices include a 2.5-V, 5-ppm/˚C internal

reference, giving full-scale output voltage ranges of

1.25 V, 2.5 V, or 5 V. The DACx0501 incorporate a

power-on-reset circuit that makes sure the DAC

output powers up at zero scale or midscale, and

remains at that scale until a valid code is written to

the device. These devices consume a low current of

1 mA, and include a power-down feature that reduces

current consumption to typically 15 µA at 5 V.

The digital interface of the DACx0501 can be

configured to SPI or I

C mode using the SPI2C pin.

In SPI mode, the DACx0501 use a versatile 3-wire

serial interface that operates at clock rates of up to

50 MHz. In I

C mode, the DACx0501 operate in

standard (100 kbps), fast (400 kbps), and fast+

(1.0 Mbps) modes.

The DACx0501 are available in easy-to-assemble

10-pin VSSOP and small 2-mm × 2-mm, 8-pin WSON

packages. The devices are fully specified over the

industrial temperature range of –40°C to +125°C.

Device Information

(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

DAC80501

DAC70501

DAC60501

WSON (8) 2.00 mm × 2.00 mm

VSSOP (10) 3.00 mm × 3.00 mm

(1) For all available packages, see the package option addendum

at the end of the data sheet.

Functional Block Diagram Offset Trimming With the DACx0501

DAC80501

DAC70501

DAC60501

SBAS794D –NOVEMBER 2018 –REVISED FEBRUARY 2020

www.ti.com

Product Folder Links: DAC80501 DAC70501 DAC60501

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Device Comparison Table..................................... 3

6 Pin Configuration and Functions......................... 3

7 Specifications......................................................... 4

7.1 Absolute Maximum Ratings ...................................... 4

7.2 ESD Ratings.............................................................. 4

7.3 Recommended Operating Conditions....................... 4

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 5

7.6 Timing Requirements : SPI Mode............................. 9

7.7 Timing Requirements : I

C Standard Mode.............. 9

7.8 Timing Requirements : I

C Fast Mode...................... 9

7.9 Timing Requirements : I

C Fast-Mode Plus ........... 10

7.10 Typical Characteristics.......................................... 11

8 Detailed Description............................................ 20

8.1 Overview ................................................................. 20

8.2 Functional Block Diagram ....................................... 20

8.3 Feature Description................................................. 20

8.4 Device Functional Modes........................................ 23

8.5 Programming........................................................... 23

8.6 Register Map........................................................... 31

9 Application and Implementation ........................ 35

9.1 Application Information............................................ 35

9.2 Typical Application .................................................. 35

10 Power Supply Recommendations ..................... 38

11 Layout................................................................... 38

11.1 Layout Guidelines ................................................. 38

11.2 Layout Example .................................................... 38

12 Device and Documentation Support ................. 39

12.1 Documentation Support ....................................... 39

12.2 Related Links ........................................................ 39

12.3 Receiving Notification of Documentation Updates 39

12.4 Support Resources ............................................... 39

12.5 Trademarks........................................................... 39

12.6 Electrostatic Discharge Caution............................ 39

12.7 Glossary................................................................ 39

13 Mechanical, Packaging, and Orderable

Information ........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (November 2019) to Revision D Page

• Changed Figure 29 to remove broken text from x axis (typo).............................................................................................. 15

• Changed Figures 33, 34 and 35; updated for clarity............................................................................................................ 16

Changes from Revision B (August 2019) to Revision C Page

• Changed DGS (VSSOP) package from preview to production data (active) ......................................................................... 1

• Added TUE parameter for DGS package to electrical characteristics table ........................................................................... 5

• Added gain error parameter for DGS package to electrical characteristics table .................................................................. 5

• Added full-scale error parameter for DGS package to electrical characteristics table........................................................... 6

Changes from Revision A (August 2019) to Revision B Page

• Changed DAC70501 and DAC60501 devices from preview to production data (active)....................................................... 1

Changes from Original (November 2018) to Revision A Page

• Changed DAC80501 in DQF (WSON) package from advanced information (preview) to production data (active) ............. 1

1VDD 10 VREFIO

2VOUT 9 NC

3NC 8 SDIN/SDA

4AGND 7 SYNC/A0

5SPI2C 6 SCLK/SCL

Not to scale

1VDD 8 VREFIO

2VOUT 7 SDIN/SDA

3AGND 6 SYNC/A0

4SPI2C 5 SCLK/SCL

Not to scale

DAC80501

DAC70501

DAC60501

www.ti.com

SBAS794D –NOVEMBER 2018–REVISED FEBRUARY 2020

Product Folder Links: DAC80501 DAC70501 DAC60501

5 Device Comparison Table

DEVICE RESOLUTION REFERENCE POWER-ON RESET

DAC80501Z 16-Bit Internal (default) or External Zero Scale

DAC80501M 16-Bit Internal (default) or External Midscale

DAC70501Z 14-Bit Internal (default) or External Zero Scale

DAC70501M 14-Bit Internal (default) or External Midscale

DAC60501Z 12-Bit Internal (default) or External Zero Scale

DAC60501M 12-Bit Internal (default) or External Midscale

6 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

DQF Package

8-Pin WSON

Top View

Pin Functions

TYPE DESCRIPTION

NAME DGS DQF

AGND 4 3 Ground Ground reference point for all circuitry on the device.

NC 3 — — No connection. Leave floating.

NC 9 — — No connection. Leave floating.

SCLK/SCL 6 5 Input Serial interface clock. SPI or I

C mode.

SDIN/SDA 8 7 Input/output

SPI mode: Serial interface data input. Data are clocked into the input shift

C mode: Data are clocked into or out of the input register. This pin is a

bidirectional, SDA drain data line that must be connected to the supply voltage

with an external pullup resistor.

SPI2C 5 4 Input

Interface select pin.

Digital interface in SPI mode if SPI2C = 0

Digital interface in I

C mode if SPI2C = 1

SPI2C pin must be kept static after device powers up.

SYNC/A0 7 6 Input

SPI mode: Active low serial data enable. This input is the frame synchronization

signal for the serial data. When the signal goes low, the serial interface input

shift register is enabled.

C mode: Four-state address input 0.

VDD 1 1 Power Analog supply voltage (2.7 V to 5.5 V)

VOUT 2 2 Output Analog output voltage from the DAC

VREFIO 10 8 Input/output

When using the internal reference, this pin is the reference output voltage pin

(default). Reference input to the device when operating with external reference.

DAC80501

DAC70501

DAC60501

SBAS794D –NOVEMBER 2018 –REVISED FEBRUARY 2020

www.ti.com

Product Folder Links: DAC80501 DAC70501 DAC60501

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN MAX UNIT

Input voltage

VDD to AGND –0.3 6

VVREFIO to AGND –0.3 VDD + 0.3

Digital input(s) to AGND –0.3 VDD + 0.3

Output voltage VOUT to AGND –0.3 VDD + 0.3 V

Input current Current into any pin –10 10 mA

Temperature

Junction temperature (T

) –40 150

°C

Storage temperature (T

stg

) –65 150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-

001, all pins

(1)

±2000

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins

(2)

±1000

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

POWER SUPPLY

VDD to AGND Positive supply voltage to ground 2.7 5.5 V

DIGITAL INPUTS

VIH Input high voltage 1.62 V

VIL Input low voltage 0.45 V

REFERENCE INPUT

VREFIO to AGND

2.7 V ≤ VDD < 3.3 V,

reference divider disabled (REF-DIV bit = 0)

1.2 0.5 × (VDD – 0.2) V

VREFIO to AGND

2.7 V ≤ VDD < 3.3 V,

reference divider enabled (REF-DIV bit = 1)

2.4 (VDD – 0.2) V

VREFIO to AGND

3.3 V ≤ VDD ≤ 5.5 V,

reference divider disabled (REF-DIV bit = 0)

1.2 0.5 × VDD V

VREFIO to AGND

3.3 V ≤ VDD ≤ 5.5 V,

reference divider enabled (REF-DIV bit = 1)

2.4 VDD V

TEMPERATURE

Operating temperature –40 125 °C

DAC80501

DAC70501

DAC60501

www.ti.com

SBAS794D –NOVEMBER 2018–REVISED FEBRUARY 2020

Product Folder Links: DAC80501 DAC70501 DAC60501

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.4 Thermal Information

THERMAL METRIC

(1)

DACx0501

UNITDGS (VSSOP) DQF (WSON)

10 PINS 8 PINS

θJA

Junction-to-ambient thermal resistance 170.1 122.6 °C/W

θJC(top)

Junction-to-case (top) thermal resistance 60.5 58.3 °C/W

θJB

Junction-to-board thermal resistance 92.6 50 °C/W

Junction-to-top characterization parameter 7.8 1.5 °C/W

Junction-to-board characterization parameter 90.7 49.8 °C/W

(1) End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12 bit, DAC output

unloaded, performance under resistive and capacitice load conditions are specified by design and characterization, DAC output range ≥

2.5 V.

7.5 Electrical Characteristics

all minimum and maximum values at T

= –40°C to +125°C and all typcal values at T

= 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external

or internal VREFIO = 1.25 V to 5.5 V , R

LOAD

= 2 kΩ to AGND, C

LOAD

= 200 pF to AGND, and digital inputs at VDD or AGND

(unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution

DAC80501 16

BitsDAC70501 14

DAC60501 12

INL Integral nonlinearity

(1)

–1 1 LSB

DNL Differential nonlinearity

(1)

–1 1 LSB

TUE Total unadjusted error

(1)

DAC80501,

reference divider disabled (REF-DIV bit = 0)

–0.08 -0.02 0.08

%FSR

DAC80501,

reference divider enabled (REF-DIV bit = 1)

–0.06 0.025 0.06

DAC80501, DGS package

reference divider enabled (REF-DIV bit = 1)

–0.07 0.025 0.07

DAC70501, DAC60501 –0.1 0.04 0.1

Zero code error

(1)

DAC loaded with zero scale code –1.5 0.5 1.5 mV

Zero code error temperature

coefficient

(1)

±2 µV/°C

Offset error

(1)

–1.5 0.5 1.5 mV

Offset error temperature

coefficient

(1)

±2 µV/°C

Gain error

(1)

DAC80501,

reference divider disabled (REF-DIV bit = 0)

–0.08 -0.02 0.08

%FSR

DAC80501,

reference divider enabled (REF-DIV bit = 1)

–0.06 0.025 0.06

DAC80501, DGS package

reference divider enabled (REF-DIV bit = 1)

–0.07 0.025 0.07

DAC70501, DAC60501 –0.1 0.04 0.1

Gain error temperature

coefficient

(1)

±1

ppm

FSR/°C

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weixin_46843154

2021-10-22

上当了我草，就是一个PDF文件，各位不要再下载了。骗钱骗积分
yiyi分析亲密关系

2023-06-12

总体评价良好，对于熟悉该领域的人来说必不可少。
StoneChan

2023-06-12

提供的代码和篇幅较长，有耐心的人可以仔细研究。
有只风车子

2023-06-12

很清晰地阐述了一些重要的概念，对初学者比较友好。
晕过前方

2023-06-12

学习这个文件需要一定的基础，不太适合完全的新手。

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