/*****************************************************************************/
/* FILE NAME: intc_SW_mode_isr_vectors_MPC5748G.c COPYRIGHT(c) Freescale 2013*/
/* All Rights Reserved */
/* DESCRIPTION: MPC5748G ISR vectors for INTC in software vector mode */
/* Based on MPC5748G ref manual rev 1 Table 20-1. */
/* USAGE: For desired vector #, replace "dummy" with ISR name and declare */
/* your isr name extern like the example below: */
/* extern void MyPeripheralISR(void); */
/* */
/*****************************************************************************/
/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
/* --- ----------- ---------- --------------------- */
/* 1.0 S Mihalik 10 Sep 2013 Initial version */
/* 1.1 D Haro 12 Feb 2014 Added SW IRQ 1 */
/*****************************************************************************/
#include "typedefs.h"
/*========================================================================*/
/* PROTOTYPES */
/*========================================================================*/
void dummy (void);
/*========================================================================*/
/* GLOBAL VARIABLES */
/*========================================================================*/
const uint32_t __attribute__ ((section (".intc_vector_table"))) IntcIsrVectorTable[] = {
(uint32_t) &dummy, /* Vector # 0 Software setable flag 0 SSCIR0[CLR0] */
(uint32_t) &dummy, /* Vector # 1 Software setable flag 1 SSCIR0[CLR1] */
(uint32_t) &dummy, /* Vector # 2 Software setable flag 2 SSCIR0[CLR2] */
(uint32_t) &dummy, /* Vector # 3 Software setable flag 3 SSCIR0[CLR3] */
(uint32_t) &dummy, /* Vector # 4 Software setable flag 4 SSCIR0[CLR4] */
(uint32_t) &dummy, /* Vector # 5 Software setable flag 5 SSCIR0[CLR5] */
(uint32_t) &dummy, /* Vector # 6 Software setable flag 6 SSCIR0[CLR6] */
(uint32_t) &dummy, /* Vector # 7 Software setable flag 7 SSCIR0[CLR7] */
(uint32_t) &dummy, /* Vector # 8 Software setable flag 8 SSCIR0[CLR8] */
(uint32_t) &dummy, /* Vector # 9 Software setable flag 9 SSCIR0[CLR9] */
(uint32_t) &dummy, /* Vector # 10 Software setable flag 10 SSCIR0[CLR10] */
(uint32_t) &dummy, /* Vector # 11 Software setable flag 11 SSCIR0[CLR11] */
(uint32_t) &dummy, /* Vector # 12 Software setable flag 12 SSCIR0[CLR12] */
(uint32_t) &dummy, /* Vector # 13 Software setable flag 13 SSCIR0[CLR13] */
(uint32_t) &dummy, /* Vector # 14 Software setable flag 14 SSCIR0[CLR14] */
(uint32_t) &dummy, /* Vector # 15 Software setable flag 15 SSCIR0[CLR15] */
(uint32_t) &dummy, /* Vector # 16 Software setable flag 16 SSCIR0[CLR16] */
(uint32_t) &dummy, /* Vector # 17 Software setable flag 17 SSCIR0[CLR17] */
(uint32_t) &dummy, /* Vector # 18 Software setable flag 18 SSCIR0[CLR18] */
(uint32_t) &dummy, /* Vector # 19 Software setable flag 19 SSCIR0[CLR19] */
(uint32_t) &dummy, /* Vector # 20 Software setable flag 20 SSCIR0[CLR20] */
(uint32_t) &dummy, /* Vector # 21 Software setable flag 21 SSCIR0[CLR21] */
(uint32_t) &dummy, /* Vector # 22 Software setable flag 22 SSCIR0[CLR22] */
(uint32_t) &dummy, /* Vector # 23 Software setable flag 23 SSCIR0[CLR23] */
(uint32_t) &dummy, /* Vector # 24 */
(uint32_t) &dummy, /* Vector # 25 */
(uint32_t) &dummy, /* Vector # 26 */
(uint32_t) &dummy, /* Vector # 27 */
(uint32_t) &dummy, /* Vector # 28 */
(uint32_t) &dummy, /* Vector # 29 */
(uint32_t) &dummy, /* Vector # 30 */
(uint32_t) &dummy, /* Vector # 31 */
(uint32_t) &dummy, /* Vector # 32 Platform watchdog timer0 SWT_0_IR[TIF] */
(uint32_t) &dummy, /* Vector # 33 Platform watchdog timer1 SWT_1_IR[TIF] */
(uint32_t) &dummy, /* Vector # 34 Platform watchdog timer2 SWT_2_IR[TIF] */
(uint32_t) &dummy, /* Vector # 35 */
(uint32_t) &dummy, /* Vector # 36 On-Platform periodic timer 0_0 (STM) STM_0_CIR0[CIF] */
(uint32_t) &dummy, /* Vector # 37 On-Platform periodic timer 0_1 (STM) STM_0_CIR1[CIF] */
(uint32_t) &dummy, /* Vector # 38 On-Platform periodic timer 0_2 (STM) STM_0_CIR2[CIF] */
(uint32_t) &dummy, /* Vector # 39 On-Platform periodic timer 0_3 (STM) STM_0_CIR3[CIF] */
(uint32_t) &dummy, /* Vector # 40 On-Platform periodic timer 1_0 (STM) STM_1_CIR0[CIF] */
(uint32_t) &dummy, /* Vector # 41 On-Platform periodic timer 1_1 (STM) STM_1_CIR1[CIF] */
(uint32_t) &dummy, /* Vector # 42 On-Platform periodic timer 1_2 (STM) STM_1_CIR2[CIF] */
(uint32_t) &dummy, /* Vector # 43 On-Platform periodic timer 1_3 (STM) STM_1_CIR3[CIF] */
(uint32_t) &dummy, /* Vector # 44 On-Platform periodic timer 2_0 (STM) STM_2_CIR0[CIF] */
(uint32_t) &dummy, /* Vector # 45 On-Platform periodic timer 2_1 (STM) STM_2_CIR1[CIF] */
(uint32_t) &dummy, /* Vector # 46 On-Platform periodic timer 2_2 (STM) STM_2_CIR2[CIF] */
(uint32_t) &dummy, /* Vector # 47 On-Platform periodic timer 2_3 (STM) STM_2_CIR3[CIF] */
(uint32_t) &dummy, /* Vector # 48 */
(uint32_t) &dummy, /* Vector # 49 */
(uint32_t) &dummy, /* Vector # 50 */
(uint32_t) &dummy, /* Vector # 51 */
(uint32_t) &dummy, /* Vector # 52 eDMA Combined Error eDMA Channel Error Flags 63-0 */
(uint32_t) &dummy, /* Vector # 53 eDMA Channel 0 DMA_INTL[INT0] */
(uint32_t) &dummy, /* Vector # 54 eDMA Channel 1 DMA_INTL[INT1] */
(uint32_t) &dummy, /* Vector # 55 eDMA Channel 2 DMA_INTL[INT2] */
(uint32_t) &dummy, /* Vector # 56 eDMA Channel 3 DMA_INTL[INT3] */
(uint32_t) &dummy, /* Vector # 57 eDMA Channel 4 DMA_INTL[INT4] */
(uint32_t) &dummy, /* Vector # 58 eDMA Channel 5 DMA_INTL[INT5] */
(uint32_t) &dummy, /* Vector # 59 eDMA Channel 6 DMA_INTL[INT6] */
(uint32_t) &dummy, /* Vector # 60 eDMA Channel 7 DMA_INTL[INT7] */
(uint32_t) &dummy, /* Vector # 61 eDMA Channel 8 DMA_INTL[INT8] */
(uint32_t) &dummy, /* Vector # 62 eDMA Channel 9 DMA_INTL[INT9] */
(uint32_t) &dummy, /* Vector # 63 eDMA Channel 10 DMA_INTL[INT10] */
(uint32_t) &dummy, /* Vector # 64 eDMA Channel 11 DMA_INTL[INT11] */
(uint32_t) &dummy, /* Vector # 65 eDMA Channel 12 DMA_INTL[INT12] */
(uint32_t) &dummy, /* Vector # 66 eDMA Channel 13 DMA_INTL[INT13] */
(uint32_t) &dummy, /* Vector # 67 eDMA Channel 14 DMA_INTL[INT14] */
(uint32_t) &dummy, /* Vector # 68 eDMA Channel 15 DMA_INTL[INT15] */
(uint32_t) &dummy, /* Vector # 69 eDMA Channel 16 DMA_INTL[INT16] */
(uint32_t) &dummy, /* Vector # 70 eDMA Channel 17 DMA_INTL[INT17] */
(uint32_t) &dummy, /* Vector # 71 eDMA Channel 18 DMA_INTL[INT18] */
(uint32_t) &dummy, /* Vector # 72 eDMA Channel 19 DMA_INTL[INT19] */
(uint32_t) &dummy, /* Vector # 73 eDMA Channel 20 DMA_INTL[INT20] */
(uint32_t) &dummy, /* Vector # 74 eDMA Channel 21 DMA_INTL[INT21] */
(uint32_t) &dummy, /* Vector # 75 eDMA Channel 22 DMA_INTL[INT22] */
(uint32_t) &dummy, /* Vector # 76 eDMA Channel 23 DMA_INTL[INT23] */
(uint32_t) &dummy, /* Vector # 77 eDMA Channel 24 DMA_INTL[INT24] */
(uint32_t) &dummy, /* Vector # 78 eDMA Channel 25 DMA_INTL[INT25] */
(uint32_t) &dummy, /* Vector # 79 eDMA Channel 26 DMA_INTL[INT26] */
(uint32_t) &dummy, /* Vector # 80 eDMA Channel 27 DMA_INTL[INT27] */
(uint32_t) &dummy, /* Vector # 81 eDMA Channel 28 DMA_INTL[INT28] */
(uint32_t) &dummy, /* Vector # 82 eDMA Channel 29 DMA_INTL[INT29] */
(uint32_t) &dummy, /* Vector # 83 eDMA Channel 30 DMA_INTL[INT30] */
(uint32_t) &dummy, /* Vector # 84 eDMA Channel 31 DMA_INTL[INT31] */
(uint32_t) &dummy, /* Vector # 85 */
(uint32_t) &dummy, /* Vector # 86 */
(uint32_t) &dummy, /* Vector # 87 */
(uint32_t) &dummy, /* Vector # 88 */
(uint32_t) &dummy, /* Vector # 89 */
(uint32_t) &dummy, /* Vector # 90 */
(uint32_t) &dummy, /* Vector # 91 */
(uint32_t) &d
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spi_NXPMPC5748G_spi_例程_源码
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spi.rar (64个子文件)
spi_Z4_2
include
derivative.h 204B
typedefs.h 4KB
MPC5748G.h 1.69MB
.settings
com.freescale.s32ds.cross.sdk.support.prefs 160B
language.settings.xml 2KB
com.freescale.s32ds.cross.core.prefs 43B
com.freescale.s32ds.cross.wizard.prefs 81B
src
MPC57xx__Interrupt_Init.c 7KB
Vector.c 3KB
intc_sw_handlers.S 3KB
intc_SW_mode_isr_vectors_MPC5748G.c 45KB
spi_Z4_2.c 439B
.project 848B
.cproject 48KB
Project_Settings
Startup_Code
startup.S 8KB
Linker_Files
sections.ld 2KB
libs.ld 88B
mem.ld 547B
Debugger
spi_Z4_2_Debug.launch 15KB
spi_Z4_1
include
derivative.h 204B
project.h 10KB
spi.h 221B
mode.h 246B
typedefs.h 4KB
MPC5748G.h 1.69MB
.settings
com.freescale.s32ds.cross.sdk.support.prefs 160B
language.settings.xml 2KB
com.freescale.s32ds.cross.core.prefs 43B
com.freescale.s32ds.cross.wizard.prefs 81B
src
flashrchw.c 2KB
MPC57xx__Interrupt_Init.c 7KB
Vector.c 3KB
spi.c 4KB
mode.c 4KB
intc_sw_handlers.S 3KB
spi_Z4_1.c 4KB
intc_SW_mode_isr_vectors_MPC5748G.c 45KB
.project 848B
.cproject 50KB
Project_Settings
Startup_Code
startup.S 8KB
Linker_Files
sections.ld 2KB
libs.ld 88B
mem.ld 547B
Debugger
spi_LaunchGroup.launch 1KB
spi_Z4_1_Debug.launch 15KB
spi_Z2_3
include
derivative.h 204B
typedefs.h 4KB
MPC5748G.h 1.69MB
.settings
com.freescale.s32ds.cross.sdk.support.prefs 160B
language.settings.xml 2KB
com.freescale.s32ds.cross.core.prefs 43B
com.freescale.s32ds.cross.wizard.prefs 81B
src
MPC57xx__Interrupt_Init.c 7KB
Vector.c 3KB
intc_sw_handlers.S 3KB
spi_Z2_3.c 369B
intc_SW_mode_isr_vectors_MPC5748G.c 45KB
.project 848B
.cproject 46KB
Project_Settings
Startup_Code
startup.S 8KB
Linker_Files
sections.ld 2KB
libs.ld 88B
mem.ld 547B
Debugger
spi_Z2_3_Debug.launch 15KB
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