pata_sis.rar_V2

/* * pata_sis.c - SiS ATA driver * * (C) 2005 Red Hat * (C) 2007,2009 Bartlomiej Zolnierkiewicz * * Based upon linux/drivers/ide/pci/sis5513.c * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> * SiS Taiwan : for direct support and hardware. * Daniela Engert : for initial ATA100 advices and numerous others. * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : * for checking code correctness, providing patches. * Original tests and design on the SiS620 chipset. * ATA100 tests and design on the SiS735 chipset. * ATA16/33 support from specs * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> * * * TODO * Check MWDMA on drives that don't support MWDMA speed pio cycles ? * More Testing */ #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/blkdev.h> #include <linux/delay.h> #include <linux/device.h> #include <scsi/scsi_host.h> #include <linux/libata.h> #include <linux/ata.h> #include "sis.h" #define DRV_NAME "pata_sis" #define DRV_VERSION "0.5.2" struct sis_chipset { u16 device; /* PCI host ID */ const struct ata_port_info *info; /* Info block */ /* Probably add family, cable detect type etc here to clean up code later */ }; struct sis_laptop { u16 device; u16 subvendor; u16 subdevice; }; static const struct sis_laptop sis_laptop[] = { /* devid, subvendor, subdev */ { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ /* end marker */ { 0, } }; static int sis_short_ata40(struct pci_dev *dev) { const struct sis_laptop *lap = &sis_laptop[0]; while (lap->device) { if (lap->device == dev->device && lap->subvendor == dev->subsystem_vendor && lap->subdevice == dev->subsystem_device) return 1; lap++; } return 0; } /** * sis_old_port_base - return PCI configuration base for dev * @adev: device * * Returns the base of the PCI configuration registers for this port * number. */ static int sis_old_port_base(struct ata_device *adev) { return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); } /** * sis_port_base - return PCI configuration base for dev * @adev: device * * Returns the base of the PCI configuration registers for this port * number. */ static int sis_port_base(struct ata_device *adev) { struct ata_port *ap = adev->link->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); int port = 0x40; u32 reg54; /* If bit 30 is set then the registers are mapped at 0x70 not 0x40 */ pci_read_config_dword(pdev, 0x54, &reg54); if (reg54 & 0x40000000) port = 0x70; return port + (8 * ap->port_no) + (4 * adev->devno); } /** * sis_133_cable_detect - check for 40/80 pin * @ap: Port * @deadline: deadline jiffies for the operation * * Perform cable detection for the later UDMA133 capable * SiS chipset. */ static int sis_133_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u16 tmp; /* The top bit of this register is the cable detect bit */ pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); if ((tmp & 0x8000) && !sis_short_ata40(pdev)) return ATA_CBL_PATA40; return ATA_CBL_PATA80; } /** * sis_66_cable_detect - check for 40/80 pin * @ap: Port * * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 * SiS IDE controllers. */ static int sis_66_cable_detect(struct ata_port *ap) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 tmp; /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ pci_read_config_byte(pdev, 0x48, &tmp); tmp >>= ap->port_no; if ((tmp & 0x10) && !sis_short_ata40(pdev)) return ATA_CBL_PATA40; return ATA_CBL_PATA80; } /** * sis_pre_reset - probe begin * @link: ATA link * @deadline: deadline jiffies for the operation * * Set up cable type and use generic probe init */ static int sis_pre_reset(struct ata_link *link, unsigned long deadline) { static const struct pci_bits sis_enable_bits[] = { { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ }; struct ata_port *ap = link->ap; struct pci_dev *pdev = to_pci_dev(ap->host->dev); if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) return -ENOENT; /* Clear the FIFO settings. We can't enable the FIFO until we know we are poking at a disk */ pci_write_config_byte(pdev, 0x4B, 0); return ata_sff_prereset(link, deadline); } /** * sis_set_fifo - Set RWP fifo bits for this device * @ap: Port * @adev: Device * * SIS chipsets implement prefetch/postwrite bits for each device * on both channels. This functionality is not ATAPI compatible and * must be configured according to the class of device present */ static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); u8 fifoctrl; u8 mask = 0x11; mask <<= (2 * ap->port_no); mask <<= adev->devno; /* This holds various bits including the FIFO control */ pci_read_config_byte(pdev, 0x4B, &fifoctrl); fifoctrl &= ~mask; /* Enable for ATA (disk) only */ if (adev->class == ATA_DEV_ATA) fifoctrl |= mask; pci_write_config_byte(pdev, 0x4B, fifoctrl); } /** * sis_old_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Device we are configuring for. * * Set PIO mode for device, in host controller PCI config space. This * function handles PIO set up for all chips that are pre ATA100 and * also early ATA100 devices. * * LOCKING: * None (inherited from caller). */ static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); int port = sis_old_port_base(adev); u8 t1, t2; int speed = adev->pio_mode - XFER_PIO_0; static const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; static const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; sis_set_fifo(ap, adev); pci_read_config_byte(pdev, port, &t1); pci_read_config_byte(pdev, port + 1, &t2); t1 &= ~0x0F; /* Clear active/recovery timings */ t2 &= ~0x07; t1 |= active[speed]; t2 |= recovery[speed]; pci_write_config_byte(pdev, port, t1); pci_write_config_byte(pdev, port + 1, t2); } /** * sis_100_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Device we are configuring for. * * Set PIO mode for device, in host controller PCI config space. This * function handles PIO set up for ATA100 devices and early ATA133. * * LOCKING: * None (inherited from caller). */ static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); int port = sis_old_port_base(adev); int speed = adev->pio_mode - XFER_PIO_0; static const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; sis_set_fifo(ap, adev); pci_write_config_byte(pdev, port, actrec[speed]); } /** * sis_133_set_piomode - Initialize host controller PATA PIO timings * @ap: Port whose timings we are configuring * @adev: Device we are configuring for. * * Set PIO mode for device, in host controller PCI config space. This * function handles PIO set up for the later ATA133 devices. * * LOCKING: * None (inherited from caller). */ static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) { struct pci_dev *pdev = to_pci_dev(ap->host->dev); int port; u32 t1; int speed = adev->pio_mode - XFER_PIO_0; static const u32 timing133[] = { 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 0x0C266000, 0x04263000, 0x0C0A3000, 0x05093000 }; static const u32 timing100[] = { 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ 0x091C4000, 0x031C2000, 0x09072000, 0x04062000 }; sis_set_fifo(ap,