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<TITLE>Assembler report for standard</TITLE>
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<H1>Assembler report for standard</H1>
<H3>Wed Apr 20 20:43:52 2005<BR>
Version 5.0 Build 146 04/13/2005 SJ Full Version</H3>
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<P><HR></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Table of Contents</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<OL>
<LI><A HREF="#1">Legal Notice</A></LI>
<LI><A HREF="#2">Assembler Summary</A></LI>
<LI><A HREF="#3">Assembler Settings</A></LI>
<LI><A HREF="#4">Assembler Generated Files</A></LI>
<LI><A HREF="#5">Assembler Device Options: c:/Pabst/test_scratch/test/standard/standard.sof</A></LI>
<LI><A HREF="#6">Assembler Device Options: c:/Pabst/test_scratch/test/standard/standard.pof</A></LI>
<LI><A HREF="#7">Assembler Messages</A></LI>
</OL>
<P><A NAME="1"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Legal Notice</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
</PRE>
<P><A NAME="2"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Assembler Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle">
<TD ALIGN="LEFT">Assembler Status</TH>
<TD ALIGN="LEFT">Successful - Wed Apr 20 20:43:52 2005</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Revision Name</TD>
<TD ALIGN="LEFT">standard</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Top-level Entity Name</TD>
<TD ALIGN="LEFT">standard</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Family</TD>
<TD ALIGN="LEFT">Stratix II</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device</TD>
<TD ALIGN="LEFT">EP2S60F672C5ES</TD>
</TR>
</TABLE>
<P><A NAME="3"><HR></A></P>
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<TD><H2>Assembler Settings</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
<TH>Default Value</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate Tabular Text File (.ttf) For Target Device</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Use smart compilation</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate Serial Vector Format File (.svf) for Target Device</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate a JEDEC STAPL Format File (.jam) for Target Device</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate an uncompressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate compressed bitstreams</TD>
<TD ALIGN="LEFT">on</TD>
<TD ALIGN="LEFT">on</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Compression mode</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Clock source for configuration device</TD>
<TD ALIGN="LEFT">Internal</TD>
<TD ALIGN="LEFT">Internal</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Clock frequency of the configuration device</TD>
<TD ALIGN="LEFT">10 MHz</TD>
<TD ALIGN="LEFT">10 MHz</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Divide clock frequency by</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">JTAG user code for target device</TD>
<TD ALIGN="LEFT">Ffffffff</TD>
<TD ALIGN="LEFT">Ffffffff</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Configuration device</TD>
<TD ALIGN="LEFT">Auto</TD>
<TD ALIGN="LEFT">Auto</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">JTAG user code for configuration device</TD>
<TD ALIGN="LEFT">Ffffffff</TD>
<TD ALIGN="LEFT">Ffffffff</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Configuration device auto user code</TD>
<TD ALIGN="LEFT">off</TD>
<TD ALIGN="LEFT">off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate Raw Binary File (.rbf) For Target Device</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Hexadecimal Output File start address</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Hexadecimal Output File count direction</TD>
<TD ALIGN="LEFT">Up</TD>
<TD ALIGN="LEFT">Up</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Release clears before tri-states</TD>
<TD ALIGN="LEFT">off</TD>
<TD ALIGN="LEFT">off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Auto-restart configuration after error</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maintain Compatibility with All Stratix II MRAM Versions</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Assembler Generated Files</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>File Name</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/standard/standard.sof</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/standard/standard.pof</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/standard/standard.ttf</TD>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
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<TD><H2>Assembler Device Options: c:/Pabst/test_scratch/test/standard/standard.sof</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device </TD>
<TD ALIGN="LEFT">EP2S60F672C5ES</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">JTAG usercode </TD>
<TD ALIGN="LEFT">0xFFFFFFFF</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Checksum </TD>
<TD ALIGN="LEFT">0x00D89744 </TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
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<TD><H2>Assembler Device Options: c:/Pabst/test_scratch/test/standard/standard.pof</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Option</TH>
<TH>Setting</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Device </TD>
<TD ALIGN=