Xilinx Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: +1 408-559-7778
Fax: +1 408-559-7114
URL: www.xilinx.com/ipcenter
Support: support.xilinx.com
October 4, 2001 1
Features
• Drop-in module for Virtex™, Virtex™-E, Virtex™-II,
Virtex™-II Pro, Spartan
TM
-II, and Spartan
TM
-IIE FPGAs
• Supports data widths up to 256 bits
• Supports memory depths of up to 65,535 locations
• Memory may be implemented in either SelectRAM+ or
Distributed RAM
• Fully synchronous and independent clock domains for
thereadandwriteports
• Supports FULL and EMPTY status flags
• Optional ALMOST_FULL and ALMOST_EMPTY status
flags
• Invalid read or write requests are rejected without
affecting the FIFO state
• Four optional handshake signals (WR_ACK, WR_ERR,
RD_ACK, RD_ERR) provide feedback
(acknowledgment or rejection) in response to write and
read requests in the prior clock cycle
• Optional count vector(s) provide visibility into number of
data words currently in the FIFO, synchronized to either
clock domain
• Uses relationally placed macro (RPM) mapping and
placement technology for maximum and predictable
performance
• Incorporates Xilinx Smart-IP technology for utmost
parameterization and optimum implementation
• To be used with version 4.1i or later of the Xilinx CORE
Generator™ System
Functional Description
The Asynchronous FIFO is a First-In-First-Out memory
queue. Its control logic performs all the necessary read and
write pointer management, generates status flags, and pro-
vides optional handshake signals for interfacing with the
user logic. The individual read and write ports are fully syn-
chronous (all operations qualified by a rising clock edge),
but this FIFO does not require the read and write clocks to
be synchronized to each other.
FIFO status cannot be corrupted by invalid requests.
Requesting a read operation while the EMPTY flag is active
will not cause any change in the current sate of the FIFO.
Similarly, requesting a write operation while the FULL flag
is active will not cause any change in the current state of
the FIFO. If enabled, the RD_ERR and WR_ERR hand-
shake signals will indicate the rejection of these invalid
requests.
In addition to the EMPTY, ALMOST_EMPTY, FULL, and
ALMOST_FULL flags, a count vector can be enabled to
provide a more granular measure of the FIFO state. For the
write domain the vector is WR_COUNT[W:0], and for the
read domain it is RD_COUNT[R:0]. The width of these vec-
tors are user programmable to provide easy generation of
additional flags. For instance, a vector width of one creates
a half-full flag; a width of two creates binary-encoded quad-
rant flags, and so on. In keeping with the fully synchronous
interface, the count vector can be synchronized to either
Figure 1: Core Schematic Symbol
Asynchronous FIFO V4.0
October 4, 2001 Product Specification
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