usb.rar_FPGA USB_FPGA实现USB通信_FPGA的USB通信

/////////////////////////////////////////////////////////////////////////////// // // DataWrite_Unit.v // 数据产生模块 // 0x0000~0xffff循环 // /////////////////////////////////////////////////////////////////////////////// module DataRead_Unit ( input ReadClock, input USB_DMAing, input USB_DMADir, input InputFIFOEmpty, input [15:0] InputFIFOData, output RDEna, output [15:0] DataOut ); reg [15:0] DataBuff; always @(posedge ReadClock) if(!USB_DMAing) DataBuff <= 0; else if(!InputFIFOEmpty & !USB_DMADir) DataBuff <= InputFIFOData; else DataBuff <= DataBuff; assign RDEna = !InputFIFOEmpty & USB_DMAing & !USB_DMADir; assign DataOut = DataBuff; endmodule /////////////////////////////////////////////////////////////////////////////// // // data_unit.v // 数据产生模块 // 0x0000~0xffff循环 // /////////////////////////////////////////////////////////////////////////////// module DataWrite_Unit ( input Clock, input USB_DMAing, input USB_DMADir, input OutputFIFOFull, output FIFOWR, output [15:0] FIFOData ); reg [15:0] counter; always @(posedge Clock) if(!USB_DMAing) counter <= 0; else if(!OutputFIFOFull & USB_DMADir) counter <= counter + 16'h1; else counter <= counter; assign FIFOWR = !OutputFIFOFull & USB_DMAing & USB_DMADir; assign FIFOData = counter; endmodule module FIFO ( clock, data, rdreq, wrreq, empty, full, q); input clock; input [7:0] data; input rdreq; input wrreq; output empty; output full; output [7:0] q; wire sub_wire0; wire [7:0] sub_wire1; wire sub_wire2; wire empty = sub_wire0; wire [7:0] q = sub_wire1[7:0]; wire full = sub_wire2; scfifo scfifo_component ( .rdreq (rdreq), .clock (clock), .wrreq (wrreq), .data (data), .empty (sub_wire0), .q (sub_wire1), .full (sub_wire2) // synopsys translate_off , .aclr (), .almost_empty (), .almost_full (), .sclr (), .usedw () // synopsys translate_on ); defparam scfifo_component.add_ram_output_register = "OFF", scfifo_component.intended_device_family = "Cyclone", scfifo_component.lpm_numwords = 256, scfifo_component.lpm_showahead = "OFF", scfifo_component.lpm_type = "scfifo", scfifo_component.lpm_width = 8, scfifo_component.lpm_widthu = 8, scfifo_component.overflow_checking = "ON", scfifo_component.underflow_checking = "ON", scfifo_component.use_eab = "ON"; endmodule module FIFO ( clock, data, rdreq, wrreq, empty, full, q); input clock; input [7:0] data; input rdreq; input wrreq; output empty; output full; output [7:0] q; endmodule module InputFIFO ( data, rdclk, rdreq, wrclk, wrreq, q, rdempty, wrfull); input [15:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [15:0] q; output rdempty; output wrfull; wire sub_wire0; wire sub_wire1; wire [15:0] sub_wire2; wire rdempty = sub_wire0; wire wrfull = sub_wire1; wire [15:0] q = sub_wire2[15:0]; dcfifo dcfifo_component ( .wrclk (wrclk), .rdreq (rdreq), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrfull (sub_wire1), .q (sub_wire2) // synopsys translate_off , .aclr (), .rdfull (), .rdusedw (), .wrempty (), .wrusedw () // synopsys translate_on ); defparam dcfifo_component.add_ram_output_register = "OFF", dcfifo_component.clocks_are_synchronized = "FALSE", dcfifo_component.intended_device_family = "Cyclone", dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 16, dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON", dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON"; endmodule module InputFIFO ( data, rdclk, rdreq, wrclk, wrreq, q, rdempty, wrfull); input [15:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [15:0] q; output rdempty; output wrfull; endmodule module IO_Unit ( input Clock, input IOEna, input IOWR, input IORD, output [7:0] IO_LED, inout [7:0] IODataBus ); reg [7:0] vdLED; //============================================================================= always @(posedge Clock) if(IOWR) vdLED <= IODataBus; else vdLED <= vdLED; assign IO_LED = vdLED; assign IODataBus = (IOEna & IORD) ? 8'h55 : 8'hzz; //============================================================================= endmodule module LED_Unit ( input Clock, input IOEna, input [7:0] IO_LED, input USB_DMADir, output [7:0] LED ); reg [7:0] vdLED; reg [23:0] Div_Counter; reg [7:0] DMALED; wire LEDEna; always @(posedge Clock) if(IOEna) Div_Counter <= 0; else if(Div_Counter == 24'h7a1200) Div_Counter <= 0; else Div_Counter <= Div_Counter + 24'h1; assign LEDEna = (Div_Counter == 24'h7a1200); always @(posedge Clock) if(IOEna) DMALED <= 8'h01; else if(LEDEna) begin if(USB_DMADir) DMALED <= {DMALED[6:0],DMALED[7]}; else DMALED <= {DMALED[0],DMALED[7:1]}; end else DMALED <= DMALED; always @(posedge Clock) if(IOEna) vdLED <= IO_LED; else vdLED <= DMALED; assign LED = vdLED; endmodule module OutputFIFO ( data, rdclk, rdreq, wrclk, wrreq, q, rdempty, wrfull); input [15:0] data; input rdclk; input rdreq; input wrclk; input wrreq; output [15:0] q; output rdempty; output wrfull; wire sub_wire0; wire sub_wire1; wire [15:0] sub_wire2; wire rdempty = sub_wire0; wire wrfull = sub_wire1; wire [15:0] q = sub_wire2[15:0]; dcfifo dcfifo_component ( .wrclk (wrclk), .rdreq (rdreq), .rdclk (rdclk), .wrreq (wrreq), .data (data), .rdempty (sub_wire0), .wrfull (sub_wire1), .q (sub_wire2) // synopsys translate_off , .aclr (), .rdfull (), .rdusedw (), .wrempty (), .wrusedw () // synopsys translate_on ); defparam dcfifo_component.add_ram_output_register = "OFF", dcfifo_component.clocks_are_synchronized = "FALSE", dcfifo_component.intended_device_family = "Cyclone", dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "OFF", dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 16, dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON", dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON"; endmodule module PLL ( inclk0, c0); input inclk0; output c0; endmodule //////////////////////////////////////////////////////////////////////////////////////////////////// // // clock_div.v // 时钟分频模块 // counter为分频系数计算器 // // //////////////////////////////////////////////////////////////////////////////////////////////////// module ReadClock_Div ( input Clock, input USB_DMAing, output Fclk ); parameter DIV_COE = 256; reg [15:0] counter; reg clk_r; always @(posedge Clock) if(!USB_DMAing) counter <= 0; else if(counter == DIV_COE) counter <= 0; else counter <= counter + 16'h1; always @(posedge Clock) if(!USB_DMAing) clk_r <= 0; else if(counter == DIV_COE) clk_r <= !clk_r; else clk_r <= clk_r; assign Fclk = clk_r; endmodule //////////////////////////////////////////////////////////////////////////////// // // USB20D_interface.v // USB20D接口信号转换模块 // 实现IO模式与DMA模式的信号转换 // //