VHDL 数字电压表 (在实验箱验证通过) wenyuzi2006年07月14日 星期五 下午 11:35附 录
源程序 和 仿真波形图
――AD控制
LIBRARY ieee; --A/D0809
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ad is
port(ST,eoc:in std_logic; --控制端口
d:in std_logic_vector(7 downto 0);
oe,sta,ale,adda:out std_logic;
q:out std_logic_vector(7 downto 0));
end ad;
architecture a of ad is
type states is(st0,st1,st2,st3,st4,st5,st6); --7个状态
signal c_state,n_state:states :=st0;
signal regl:std_logic_vector(7 downto 0);
signal lock:std_logic;
begin
adda<='1';
com:process(c_state,eoc)
begin
case c_state is
when st0=>ale<='0';sta<='0';oe<='0';lock<='0';
n_state<=st1;
when st1=>ale<='1';sta<='0';oe<='0';lock<='0';
n_state<=st2;
when st2=>ale<='0';sta<='1';oe<='0';lock<='0';
n_state<=st3;
when st3=>ale<='0';sta<='0';oe<='0';lock<='0';
if(eoc='1') then n_state<=st4;
else n_state<=st3; ――eoc为‘1’转换结束 进入下一状态
end if; ――否则 继续转换
when st4=>ale<='0';sta<='0';oe<='1';lock<='0';
n_state<=st5;
when st5=>ale<='0';sta<='0';oe<='0';lock<='1';
n_state<=st6;
when st6=>ale<='0';sta<='0';oe<='0';lock<='1';
n_state<=st0;
when others=>n_state<=st0;
end case;
end process com;
reg:process(st)
begin
if(st'event and st='1') then
c_state<=n_state;
end if;
end process reg;
lo:process(lock) --锁存
begin
if(lock'event and lock='1') then
regl<=d;
end if;
end process lo;
q<=regl;
end a;
――BCD 8位转12
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD IS
PORT (V:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
HB,LB:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0);
BVALUE:BUFFER STD_LOGIC_VECTOR(11 DOWNTO 0);
BCD_L,BCD_M,BCD_H:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END BCD;
ARCHITECTURE A OF BCD IS
BEGIN
P1:PROCESS(V(7 DOWNTO 4))
BEGIN --A/D输出高4位转换 分辨率0.32V
IF V(7 DOWNTO 4)="1111" THEN HB<="010010000000"; --4.80V
ELSIF V(7 DOWNTO 4)= "1110" THEN HB<="010001001000";--4.48V
ELSIF V(7 DOWNTO 4)= "1101" THEN HB<="010000010110";--4.16V
ELSIF V(7 DOWNTO 4)= "1100" THEN HB<="001110000100";--3.84V
ELSIF V(7 DOWNTO 4)= "1011" THEN HB<="001101010010";--3.52V
ELSIF V(7 DOWNTO 4)= "1010" THEN HB<="001100100000";--3.20V
ELSIF V(7 DOWNTO 4)= "1001" THEN HB<="001010001000";--2.88V
ELSIF V(7 DOWNTO 4)= "1000" THEN HB<="001001010110";--2.56V
ELSIF V(7 DOWNTO 4)= "0111" THEN HB<="001000100100";--2.24V
ELSIF V(7 DOWNTO 4)= "0110" THEN HB<="000110010010";--1.92V
ELSIF V(7 DOWNTO 4)= "0101" THEN HB<="000101100000";--1.60V
ELSIF V(7 DOWNTO 4)= "0100" THEN HB<="000100101000";--1.28V
ELSIF V(7 DOWNTO 4)= "0011" THEN HB<="000010010110";--0.96V
ELSIF V(7 DOWNTO 4)= "0010" THEN HB<="000001100100";--0.64V
ELSIF V(7 DOWNTO 4)= "0001" THEN HB<="000000110010";--0.32V
ELSIF V(7 DOWNTO 4)= "0000" THEN HB<="000000000000";--0.00V
ELSE HB<="000000000000" ; --0.00V
END IF;
END PROCESS P1;
P2:PROCESS(V(3 DOWNTO 0))
BEGIN --A/D输出低4位转换 分辨率0.02V
IF V(3 DOWNTO 0)= "1111" THEN LB<="000000110000"; --0.30V
ELSIF V(3 DOWNTO 0)= "1110" THEN LB<="000000101000";--0.28V
ELSIF V(3 DOWNTO 0)= "1101" THEN LB<="000000100110";--0.26V
ELSIF V(3 DOWNTO 0)= "1100" THEN LB<="000000100100";--0.24V
ELSIF V(3 DOWNTO 0)= "1011" THEN LB<="000000100010";--0.22V
ELSIF V(3 DOWNTO 0)= "1010" THEN LB<="000000100000";--0.20V
ELSIF V(3 DOWNTO 0)= "1001" THEN LB<="000000011000";--0.18V
ELSIF V(3 DOWNTO 0)= "1000" THEN LB<="000000010110";--0.16V
ELSIF V(3 DOWNTO 0)= "0111" THEN LB<="000000010100";--0.14V
ELSIF V(3 DOWNTO 0)= "0110" THEN LB<="000000010010";--0.12V
ELSIF V(3 DOWNTO 0)= "0101" THEN LB<="000000010000";--0.10V
ELSIF V(3 DOWNTO 0)= "0100" THEN LB<="000000001000";--0.08V
ELSIF V(3 DOWNTO 0)= "0011" THEN LB<="000000000110";--0.06V
ELSIF V(3 DOWNTO 0)= "0010" THEN LB<="000000000100";--0.04V
ELSIF V(3 DOWNTO 0)= "0001" THEN LB<="000000000010";--0.02V
ELSIF V(3 DOWNTO 0)= "0000" THEN LB<="000000000000";--0.00V
ELSE LB<="000000000000"; --0V
END IF;
END PROCESS P2;
BVALUE<=HB+LB;
P3:PROCESS(BVALUE)
VARIABLE JJ:STD_LOGIC_VECTOR(11 DOWNTO 0);
BEGIN
JJ:=BVALUE;
IF (JJ(3 DOWNTO 0)>"1001") THEN ――如果12位结果中,低4位
JJ:=JJ+"000000000110"; ――大于9 则低4位加6
END IF;
IF(JJ(7 DOWNTO 4)>"1001") THEN ――如果中间的4位大于9
JJ:=JJ+"000001100000"; ――则中4位加6
END IF;
BCD_L<=JJ(3 DOWNTO 0);
BCD_M<=JJ(7 DOWNTO 4);
BCD_H<=JJ(11 DOWNTO 8);
END PROCESS P3;
END A;
――3选1 数据选择器
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux3_1 is
port(sel:in std_logic_vector(1 downto 0);
A,B,C:in std_logic_vector(3 downto 0);
Mselout:out std_logic_vector(3 downto 0));
end mux3_1;
architecture a of mux3_1 is
begin
process(sel)
begin
if sel="10" then Mselout<=A;
elsif sel="01" then Mselout<=B;
elsif sel="00" then Mselout<=C;
else null;
end if;
end process;
end a;
――位选信号产生器(3进制计数器)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity c3 is
port(clk,clr:in std_logic;
qout:buffer std_logic_vector(1 downto 0)
);
end c3;
architecture behave of c3 is
begin
process(clk,clr)
begin
if(clr='0')then qout<="00";
elsif(clk'event and clk='1')then
qout<=qout+1;
if(qout=2)then qout<="00";
end if;
end if;
end process;
end behave;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY del7 IS
PORT
( input : IN STD_LOGIC_vector(3 downto 0);
output : OUT STD_LOGIC_vector(6 downto 0)
);
END del7;
ARCHITECTURE a OF del7 IS
BEGIN
PROCESS (input)
BEGIN
CASE input IS
WHEN "0000" =>output<="1111110";
WHEN "0001" =>output<="0110000";
WHEN "0010" =>output<="1101101";
WHEN "0011" =>output<="1111001";
WHEN "0100" =>output<="0110011";
WHEN "0101" =>output<="1011011";
WHEN "0110" =>output<="1011111";
WHEN "0111" =>output<="1110000";
WHEN "1000" =>output<="1111111";
WHEN "1001" =>output<="1111011";
WHEN OTHERS=>NULL;
END CASE;
end process;
END a;
――小数点产生器
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity DP is
port(SELDP:in std_logic_vector(1 downto 0);
DPout:out std_logic);
end DP;
architecture a of DP is
begin
process(selDP)
begin
if selDP="10" then DPout<='0';
elsif selDP="01" then DPout<='0';
elsif selDP="00" then DPout<='1'; ――在高4位整数输出时,输出
else null; ――小数点DP
end if;
end process;
end a;
――顶层文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity V_WATCH is
port( clkK,EOCC:in std_logic;
DD:IN std_logic_vector(7 downto 0);
clk3,CLR3:IN STD_LOGIC;
OEE,START,ALEE,ADDAA:OUT STD_LOGIC;
DPOUT:OUT STD_LOGIC;
Qoutput:out std_logic_vector(6 downto 0);
Qselout:out std_logic_vector(1 downto 0));
end V_WATCH;
architecture a of V_WATCH is ――元件例化
COMPONENT DP
port(SELDP:in std_logic_vector(1 downto 0);
DPout:out std_logic);
END COMPONENT;
COMPONENT del7
PORT(